132 4-bit Neural Network Accelerator :: Quicker, easier and cheaper to make your own chip!

132 : 4-bit Neural Network Accelerator

Author: timasangwan-amit

Description: A 4-bit neural network MAC accelerator with ReLU activation, supporting LOAD_BIAS, MAC, and ACTIVATE operations via a 2-bit opcode interface.

GitHub repository

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Clock: 1000000 Hz

How it works

This project implements a 4-bit neural network MAC (Multiply-Accumulate) accelerator with ReLU activation. It supports four operations controlled by a 2-bit opcode on ui_in[7:6]:

IDLE (00): Hold current state, no operation performed.
LOAD_BIAS (01): Load an 8-bit signed bias value from uio_in[7:0] into the internal accumulator.
MAC (10): Multiply a 4-bit signed weight (uio_in[7:4]) by a 4-bit signed activation/feature (uio_in[3:0]) and accumulate: accumulator += weight * feature.
ACTIVATE (11): Apply a right-shift by ui_in[2:0] bits (quantization) and then ReLU activation. Results are clamped to [0, 7]. The 4-bit result is output on uo_out[3:0].

The internal accumulator is 11 bits wide to prevent overflow during accumulation. The output register (uo_out[7:4] is always 0, the result appears in uo_out[3:0]).

How to test

Assert rst_n low for at least 10 clock cycles to reset the accumulator and output to zero.
Release reset (rst_n = 1) and verify uo_out = 0.
Load a bias: Set ui_in = 0x40 (opcode=LOAD_BIAS, shift=0) and uio_in to the desired signed bias byte. Pulse the clock.
Perform a MAC operation: Set ui_in = 0x80 (opcode=MAC) and uio_in[7:4] = weight, uio_in[3:0] = feature. Pulse the clock. Repeat for multiple MAC operations.
Activate: Set ui_in = 0xC0 | shift_val (opcode=ACTIVATE, shift=shift_val). Pulse the clock twice. Read uo_out[3:0] for the ReLU-activated quantized result.

Example: LOAD_BIAS=0, MAC(weight=3, feature=2), ACTIVATE(shift=0) → output = 6. Example: LOAD_BIAS=0, MAC(weight=-1, feature=4), ACTIVATE(shift=0) → output = 0 (ReLU clips negative).

External hardware

None required. All inputs and outputs use the standard TinyTapout IO pins.

#	Input	Output	Bidirectional
0	shift_val[0]	result[0]	feature[0]
1	shift_val[1]	result[1]	feature[1]
2	shift_val[2]	result[2]	feature[2]
3		result[3]	feature[3]
4			weight[0]
5			weight[1]
6	op_code[0]		weight[2]
7	op_code[1]		weight[3]

Input

Output

Bidirectional

shift_val[0]

result[0]

feature[0]

shift_val[1]

result[1]

feature[1]

shift_val[2]

result[2]

feature[2]

result[3]

feature[3]

weight[0]

weight[1]

op_code[0]

weight[2]

op_code[1]

weight[3]

Chip location