I recommend prepending your github username:
# bad module top ( ) # good module mattvenn_top ( )
We only support 8 ins and 8 outs and they must be named
# bad module mattvenn_counter ( input [100:0] my_bus, ); # good module mattvenn_counter ( input [7:0] io_in, output [7:0] io_out );
Tiny Tapeout is a compromise - we try to make it easy to get to ASIC, but we have to make limitations, like IO speed, IO count, size etc. If you want to go full custom then check out the Zero to ASIC course.
It can be very strange to come from programming to hardware design. Synthesis tools are trying to optimise your design for area and speed.
How can you know if your design is being optimised? Think about how much logic and flops your design needs to get a rough cell count. It’s normal for Yosys to be able to reduce this number a bit, but if it’s half as much as you expect or less, it’s worth checking.
If you have a good testbench, you can run it on the GL verilog and that will help you make sure your design is still working after synthesis.
Look at the GitHub action log for the GDS build. Check the yosys section of the build and search for warnings. Common ones include: