As we’ve seen, an NMOS inverter is inefficient because it’s wasting energy through the resistor. CMOS logic replaces the pull up resistor with a P type mosfet. As the P type is the complementary version of the N type, we call this type of logic Complementary Metal Oxide Semiconductor or CMOS for short.
There are many ways to draw this, but it’s fairly usual to use the same piece of polysilicon as the gate for both the P type and N type. If you get stuck you can check my solution here.
And the simulation shows the CMOS inverter is working nicely:
I also added the current in the simulation traces. You can see we get a little spike as the inverter operates, but in either high or low states, the current is very low. This efficiency is the reason why CMOS is still the most commonly used type of logic gates used in computer chips.
We’ve seen how to draw and make a logic inverter, but there are many other types of logic gates like AND, OR and NOT gates. Feel free to try drawing some yourself! Share your designs with us in the Discord community channel. Use the hashtag #SilliWiz on social media.
A typical PDK will include hundreds of standard cells. Here’s the Skywater 130nm inverter standard cell:
Can you identify the P and N type MOSFETs? Can you see the input and output ports? Here’s a 3D view of the same cell:
One thing that makes standard cells standard is that they all have the same height and the top and bottom always includes the power supply vdd and vss. This lets us put lots of cells all together on a grid.
Here’s a 3D view of some standard cells all together, powered by the blue vss and vdd lines.
Can you spot an inverter?
And here we see how the wires connect up the cells into a more complex digital machine:
If you want to explore this design yourself:
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SiliWiz is a project by Matt Venn. Thanks to all the testers and in particular to: