Hi, I’m a professor for an Introduction to Digital Systems course and just found this and let’s just say this has fundamentally just changed our entire Computer Engineering curriculum. It looks like we can actually have first-year students designing ASICs, then be able later to analyze performance while taking their electronics course and learning about MOSFETs as well as their embedded systems and computer architecture. Russell Trafford, Rowan University


Run Launched Closed Shuttle Designs
TT01 2022-08-17 2022-09-01 MPW7 152
TT02 2022-11-09 2022-12-02 2211Q 165
TT03 2023-03-01 2023-04-23 2304C



TT01 statistics

  • 152 projects submitted
  • Each project is 100um x 100um
  • 115 used Wokwi graphical editor, 31 Verilog, 3 XLS, 2 Chisel, 1 Amaranth
  • 15k standard cells used across all projects
  • Most cells used in a design was 600, the least was 14
  • Total wire length 772 mm

TT02 statistics

  • 165 projects submitted
  • Each project is 150 x 170um
  • Youngest submitter: 4 years old
  • 64 used Wokwi graphical editor, 82 Verilog, 5 Amaranth, 1 Chisel
  • 40k standard cells used across all projects
  • Most cells used in a design was 1105, the least was 8
  • Total wire length 2024 mm
  • Max utilisation was 52%

Project showcase

Wokwi projects

HDL projects


An educational chip development workflow entirely in-browser, from graphic entry to GDSII output for #sky130! Stunning work by @matthewvenn to make an opaque area of technology accessible.

Last week I designed an integrated circuit for #tinytapeout, my first digital circuit design not to include any kind of cpu.

I still can’t get over how smooth the ASIC design workflow of the #tinytapeout is

Thank you @matthewvenn and everyone who made #tinytapeout happen! I made a simple counter FSM based on a UTexas presentation (linked below), but I made it all on my new Steamdeck!

Created a 128-Bit Memory (8 x 16-Bit Blocks) custom ASIC. I hope it will be manufactured in next shuttle run. Aside from that, It was amazing how seamless and easy was the whole process.

I want to change my VLSI class in the spring (April-June) to utilise your tiny chip infrastructure. If I could say every student in my class got something made, that would be awesome.

Built a CRC logic for the of @matthewvenn with my son. Looking forward if the tapeout happens 🥰 Yet either way, the workflow is astonishing. CI/CD for chip design 🤯

Thank you for doing it - I always wanted to join these OpenMPW shuttles, but never felt ready for it. TinyTapeout provided a way for me to get in, while only spending 1 evening of effort on my end. That’s amazing!

Just made a 4-bit barrel shifter by using this toolkit. It’s quick and fun to use. The GDS even generated within minutes. Everyone should try this.

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