I’m stuck, how can I get support?

Join the discord community with this link.

Chip Specs for TT01, TT02 & TT03

What is the top clock speed?

We think it will be around 12.5KHz. It’s slow because we’re currently using a serial scan chain to connect all the designs. We have a built in clock divider that can further reduce this speed down to 255 times slower than the top clock speed.

We are working on a much faster mux based version here.

How many ins and outs do I get?

8 ins and 8 outs.

Chip Specs for TT04, TT05 and TT06

What is the top clock speed?

At least 50MHz. We have received silicon for our test run and are in the process of measuring it.

How many ins and outs do I get?

  • clock and nreset (low to reset)
  • 8 ins
  • 8 outs
  • 8 bidirectional ios

What PDK is used for the manufacture?

We are using the open source Skywater 130nm PDK

How big can my design be?

For TT04 to TT06, the standard tile size is about 160x100 um. This is enough for about 1000 digital logic gates, depending on their size. You can also buy extra tiles if you need more room.

Here’s a 3D view of the GDS of my 7 segment seconds counter, a small design that increments a counter every second and shows the result on the 7 segment display.

Click the picture to open an interactive viewer.

7 seg

When will the chips get manufactured?

The chips are taking between 6 and 9 months to manufacture. Then we need to do PCBA, test and order fulfillment. So expect up to 1 year’s wait time!

You can find an up to date estimate for each shuttle in the runs page.

Wokwi FAQs

How do I do x, y, z with Wokwi?

Wokwi’s documentation is here. We don’t have much documentation yet for the ASIC version of Wokwi.

Shortcut keys

  • select a component and press delete to remove it
  • select a component (or shift select to add more components), then d to duplicate it.
  • shift and drag to drag a box around multiple components
    • and - to zoom in and out
  • More here.

Can I copy and paste from one Wokwi design to another?

  1. Select all the parts you want to copy (using shift and click the parts or shift and drag a box)
  2. Copy them to clipboard (Ctrl+C or Cmd+C)
  3. Go to the target project, click on the diagram editor, and paste (Ctrl+V or Cmd+V)

How can I undo / redo?

  • Ctrl+Z & Ctrl+Y or ⌘Z / ⌘Y on a Mac.

How do I find out the wiring of the 7 segment display?

Clicking on a component will bring up a ? in a circle. Click on the ? to get the help.

Do I have to use the 7 segment?

No, you can delete it and put whatever you want there. There’s lots of other components you can choose from the + menu. But if you get a PCB, it will only have the 7 segment on it. You’d need to plug the board into a breadboard and add your extra components after.

How do I add new gates?

Either duplicate an existing one (select it and press d), or:

  • press the + button menu at the top of the page,
  • in the filter box, type ’logic’ to filter only the logic gates.

How do I move a set of gates?

Select all the ones you want to move (using shift and click the parts or shift and drag a box). Then drag the selection.

How do I use the clock block?

You can use the first input as the clock. If you need to change the clock frequency you have to do it by editing the json diagram file. Set the “frequency” attribute to the frequency you want in Hz (e.g. “10000” or “10k” for 10 KHz).

Tiny Tapeout will support a wide range of clock frequencies (we anticipate up to 50 MHz). However, to make sure Wokwi simulates your design fast enough, you should not use a clock frequency higher than 100 KHz while simulating your design.


Are there some examples of projects people have made?

Check the runs page.

Do I need to delete unused digital gates?

No, unused gates will be optimised out by the ASIC tools.

I found and fixed a problem in my design - do I need to resubmit?

Yes, you need to

Do I need to use Wokwi, or could I use an HDL?

If you’re an advanced user, you can use the HDL of your choice. See the HDL page for more information.

Tiny Tapeout FAQs

Where can I find the the template to get started?

You can access it on the Getting Started Page.

Which of my builds will be submitted for fabrication?

If you update your project and want us to use your latest version, you have to go to your submission and create a new submission.

You can keep updating your design up to the tapeout deadline.

Is it TinyTapeout or Tiny Tapeout?

It’s Tiny Tapeout. See the Branding page for more information.

Github FAQs

When I commit my change, the GDS action isn’t running

You need to enable the actions.

  1. Go to the Actions tab,
  2. Click the enable actions button.


Also see the next FAQ on the GDS action failing on ‘pages’.

My GitHub action is failing on the ‘pages’ part.

Due to Github limitations, you need to do make a change to the settings of your repository to get everything to work.

  1. Go to Settings tab,
  2. Select Pages,
  3. Change Source from Deploy from a branch to GitHub Actions.


I got an error on my GitHub GDS action.

The best way to let me know is to open an issue on the template repository with a link to your wokwi design and I’ll get back to you.

I got an error on my GitHub Documentation action.

You might not have filled in enough fields, we require the following fields to be filled:


I updated and saved my wokwi design, how do I re-run the Github action to update the GDS files?

  1. Go to your repository, click the actions tab
  2. Then click the ‘gds’ workflow
  3. Then click the ‘Run workflow’ button
  4. Then click the ‘Run workflow’ button


What are all the files in the artifact?

There are lots!

  • src - the source files for your chip:
    • user_module_xxxxx.v the Verilog file that represents your Wokwi design.
    • config.tcl - config file for the OpenLane ASIC tool flow that turns the Verilog into GDS.
    • cells.v translates the modules into the standard cells available for the Skywater 130nm process.
  • runs/wokwi/reports/metrics.csv - a detailed summary report of the tool flow. It’s beyond the scope of this doc for now to explain it all.
  • runs/wokwi/reports/synthesis/1-synthesis.stat.rpt.strategy4 report of the standard cells used for your design.
  • runs/wokwi/results/final/ (just the most important described here)
    • gds - the final GDS file that will be added to the Tiny Tapeout submission.
    • lef - an abstract version of the GDS with less information, used for routing.
    • verilog - the gate level verilog of your design.

Where is the submission repository for the shuttle?


What do all these acronyms you keep using mean?

Sorry! We are trying to keep it accessible but we’ll inevitably use some ASIC terminology at some point! See the terminology guide here.

Why do I have fewer / more standard cells than I expected?

Logic synthesis has to convert Verilog to a data structure which has specific properties so that a technology library (like Sky130) can be mapped to it, so that it can actually be fabricated.

If you have 2 inverters in series, Yosys (the synthesis tool) may well optimise them both out, so you end up with less cells than expected.

However, if you have only 8 cells, your design is probably completely optimised out. Maybe you didn’t connect the inputs or outputs?

Why is target density set to 60%? Should I change it to 100% or should I add another tile?

Routing tends to take up more space than the logic. Also, there needs to be space for OpenLane to add extra cells:

  • tap cells - make sure the substrate is correctly biased for the transistors.
  • antenna diodes - protect transitor gates during manufacture.

Some people have successfully increased the target density to around 62%. Alternatively you can buy an additional tile.

How can I learn more about ASICs and how to design them?

Check out Matt’s Zero to ASIC course!