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At least 50MHz. We have received silicon for our test run and are in the process of measuring it.
We are using the open source Skywater 130nm PDK
For TT04 to TT09, the standard tile size is about 160x100 um. This is enough for about 1000 digital logic gates, depending on their size. You can also buy extra tiles if you need more room.
Here’s a 3D view of the GDS of my 7 segment seconds counter, a small design that increments a counter every second and shows the result on the 7 segment display.
Click the picture to open an interactive viewer.
The chips are taking between 6 and 9 months to manufacture. Then we need to do PCBA, test and order fulfillment. So expect up to 1 year’s wait time!
You can find an up to date estimate for each shuttle in the runs page.
You can use our handy calculator to check pricing. The first 80 orders from individuals are sponsored by Efabless, so you get 1 tile, 1 ASIC mounted on 1 demo board PCB for $150 + postage. After those first 80 are gone, the price goes up to $300.
You only get 1 chip. If you want more chips you have to order more of the PCBs at $250 each - the early bird price is only available once per person.
Leftover chips and PCBs get put into our shop and are sold for around $75 and $250 respectively. We only sell spares, so there is no guarantee there will be any.
Wokwi’s documentation is here. We don’t have much documentation yet for the ASIC version of Wokwi.
Clicking on a component will bring up a ? in a circle. Click on the ? to get the help.
No, you can delete it and put whatever you want there. There’s lots of other components you can choose from the + menu. But if you get a PCB, it will only have the 7 segment on it. You’d need to plug the board into a breadboard and add your extra components after.
Either duplicate an existing one (select it and press d), or:
Select all the ones you want to move (using shift and click the parts or shift and drag a box). Then drag the selection.
You can use the first input as the clock. If you need to change the clock frequency you have to do it by editing the json diagram file. Set the “frequency” attribute to the frequency you want in Hz (e.g. “10000” or “10k” for 10 KHz).
Tiny Tapeout will support a wide range of clock frequencies (we anticipate up to 50 MHz). However, to make sure Wokwi simulates your design fast enough, you should not use a clock frequency higher than 100 KHz while simulating your design.
Check the runs page.
No, unused gates will be optimised out by the ASIC tools.
Yes, you need to
If you’re an advanced user, you can use the HDL of your choice. See the HDL page for more information.
You can access it on the Getting Started Page.
If you update your project and want us to use your latest version, you have to go to your submission and create a new submission.
You can keep updating your design up to the tapeout deadline.
It’s Tiny Tapeout. See the Branding page for more information.
You need to enable the actions.
Also see the next FAQ on the GDS action failing on ‘pages’.
Due to Github limitations, you need to do make a change to the settings of your repository to get everything to work.
The best way to let me know is to open an issue on the template repository with a link to your wokwi design and I’ll get back to you.
You might not have filled in enough fields, we require the following fields to be filled:
author
title
description
how_it_works
how_to_test
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There are lots!
Sorry! We are trying to keep it accessible but we’ll inevitably use some ASIC terminology at some point! See the terminology guide here.
Logic synthesis has to convert Verilog to a data structure which has specific properties so that a technology library (like Sky130) can be mapped to it, so that it can actually be fabricated.
If you have 2 inverters in series, Yosys (the synthesis tool) may well optimise them both out, so you end up with less cells than expected.
However, if you have only 8 cells, your design is probably completely optimised out. Maybe you didn’t connect the inputs or outputs?
Routing tends to take up more space than the logic. Also, there needs to be space for OpenLane to add extra cells:
Some people have successfully increased the target density to around 62%. Alternatively you can buy an additional tile.
Check out Matt’s Zero to ASIC course!
Tiny Tapeout provides a set of 24 general-purpose I/O pins: 8 are input-only (ui_in
), 8 are output-only (uo_out
) and 8 are tri-state bi-directional (uio_*
).
By default, the clk
input port is used as the main clock, generated by the on-board RP2040 chip. However, it is possible to use one of the inputs ui_in
as auxiliary clock. In this
case, special care must be taken when running the flow.
As an example, let’s assume two clocks are needed: the one generated by the RP2040 device, we name it rp2040_clk
, and an auxiliary one generated by an off-board FPGA, we name it fpga_clk
.
Both clocks have the same frequency, but clearly unknown phase (i.e., they are mesochronous). Also, let’s assume these clocks do never interact each other (i.e., no CDC). We also map
the fpga_clk
to pin ui_in[0]
.
To be able to run this scenario we need to tweak the configuration file config.tcl
that will be used by the Tiny Tapeout workflow, so that:
clk
port;The following lines are required in the config.tcl
file:
1 set ::env(CLOCK_PORT) "ui_in\\\[0\\\]"
2 set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/project.sdc"
Line 1 sets the CLOCK_PORT
name, from the (default) clk
to our ui_in[0]
. Please notice the backslash pattern here! There is no need to set the CLOCK_NET
variable to a list of clocks,
since we are using a custom constraint file, namely project.sdc
.
Then, the contents of project.sdc
are:
1 # Shared constants, copied from base.sdc
2 set input_delay_value [ expr $::env(CLOCK_PERIOD) * $::env(IO_PCT) ]
3 set output_delay_value [ expr $::env(CLOCK_PERIOD) * $::env(IO_PCT) ]
4 set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [ current_design ]
5 set cap_load [ expr $::env(OUTPUT_CAP_LOAD) / 1000.0 ] ;# fF -> pF
6
7 # Remove clock net from inputs
8 set idx [ lsearch [ all_inputs ] "clk" ]
9 set all_inputs_wo_clk [ lreplace [ all_inputs ] $idx $idx ]
10 set idx [ lsearch $all_inputs_wo_clk "ui_in\[0\]" ]
11 set all_inputs_wo_clk [ lreplace $all_inputs_wo_clk $idx $idx ]
12
13 # clk clock is generated by the RP2040 chip
14 create_clock [ get_ports "clk" ] -name rp2040_clk -period $::env(CLOCK_PERIOD)
15 set_input_delay $input_delay_value -clock [ get_clocks rp2040_clk ] $all_inputs_wo_clk
16 set_output_delay $output_delay_value -clock [ get_clocks rp2040_clk ] [ all_outputs ]
17 set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [ get_clocks rp2040_clk ]
18 set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [ get_clocks rp2040_clk ]
19
20 # ui_in[0] clock is generated by the FPGA
21 create_clock [ get_ports "ui_in\[0\]" ] -name fpga_clk -period $::env(CLOCK_PERIOD)
22 set_input_delay $input_delay_value -clock [ get_clocks fpga_clk ] $all_inputs_wo_clk
23 set_output_delay $output_delay_value -clock [ get_clocks fpga_clk ] [ all_outputs ]
24 set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [ get_clocks fpga_clk ]
25 set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [ get_clocks fpga_clk ]
26
27 # rp2040_clk and fpga_clk are mesochronous, and they never interact
28 set_clock_groups -asynchronous -group { rp2040_clk } -group { fpga_clk }
29
30 # Miscellanea
31 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) $all_inputs_wo_clk
32 set_load $cap_load [ all_outputs ]
33 set_timing_derate -early [ expr {1-$::env(SYNTH_TIMING_DERATE)} ]
34 set_timing_derate -late [ expr {1+$::env(SYNTH_TIMING_DERATE)} ]
Please be careful of the backslash pattern here! It is different than the config.tcl
case! If you run into the following error:
[ERROR]: The specified clock port 'ui_in[0]' does not exist in the top-level module.
chances are the backslashes are wrong!
The above SDC is pretty much derived from the default base.sdc
constraint file. Please remember once again that the two clocks have same frequency! The file has been organized, though:
rp2040_clk
is generated first, with its own I/O delay and uncertainty;fpga_clk
is generated next;With the above two clock trees are generated, STA analysis will be run on both clock trees and no CDC shall be found.
Please note that the above works for OpenLane tag 2023.11.23
. More recent versions that include the check_clock_ports.py
script will not work. This is due to the way the
check_clock_ports.py
works: it is not able to detect sliced ports (as in ui_in[0]
).