Join the discord community with this link.
We think it will be around 12.5KHz. It’s slow because we’re currently using a serial scan chain to connect all the designs. We have a built in clock divider that can further reduce this speed down to 255 times slower than the top clock speed.
We are working on a much faster mux based version here.
8 ins and 8 outs.
At least 50MHz. We have received silicon for our test run and are in the process of measuring it.
We are using the open source Skywater 130nm PDK
For TT04 to TT06, the standard tile size is about 160x100 um. This is enough for about 1000 digital logic gates, depending on their size. You can also buy extra tiles if you need more room.
Click the picture to open an interactive viewer.
The chips are taking between 6 and 9 months to manufacture. Then we need to do PCBA, test and order fulfillment. So expect up to 1 year’s wait time!
You can find an up to date estimate for each shuttle in the runs page.
Clicking on a component will bring up a ? in a circle. Click on the ? to get the help.
No, you can delete it and put whatever you want there. There’s lots of other components you can choose from the + menu. But if you get a PCB, it will only have the 7 segment on it. You’d need to plug the board into a breadboard and add your extra components after.
Either duplicate an existing one (select it and press d), or:
Select all the ones you want to move (using shift and click the parts or shift and drag a box). Then drag the selection.
You can use the first input as the clock. If you need to change the clock frequency you have to do it by editing the json diagram file. Set the “frequency” attribute to the frequency you want in Hz (e.g. “10000” or “10k” for 10 KHz).
Tiny Tapeout will support a wide range of clock frequencies (we anticipate up to 50 MHz). However, to make sure Wokwi simulates your design fast enough, you should not use a clock frequency higher than 100 KHz while simulating your design.
Check the runs page.
No, unused gates will be optimised out by the ASIC tools.
Yes, you need to
If you’re an advanced user, you can use the HDL of your choice. See the HDL page for more information.
You can access it on the Getting Started Page.
If you update your project and want us to use your latest version, you have to go to your submission and create a new submission.
You can keep updating your design up to the tapeout deadline.
It’s Tiny Tapeout. See the Branding page for more information.
You need to enable the actions.
Also see the next FAQ on the GDS action failing on ‘pages’.
Due to Github limitations, you need to do make a change to the settings of your repository to get everything to work.
The best way to let me know is to open an issue on the template repository with a link to your wokwi design and I’ll get back to you.
You might not have filled in enough fields, we require the following fields to be filled:
There are lots!
Sorry! We are trying to keep it accessible but we’ll inevitably use some ASIC terminology at some point! See the terminology guide here.
Logic synthesis has to convert Verilog to a data structure which has specific properties so that a technology library (like Sky130) can be mapped to it, so that it can actually be fabricated.
If you have 2 inverters in series, Yosys (the synthesis tool) may well optimise them both out, so you end up with less cells than expected.
However, if you have only 8 cells, your design is probably completely optimised out. Maybe you didn’t connect the inputs or outputs?
Routing tends to take up more space than the logic. Also, there needs to be space for OpenLane to add extra cells:
Some people have successfully increased the target density to around 62%. Alternatively you can buy an additional tile.