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Digital Design Guide
Getting started with our digital design tool
Holidays
Logic Gates
Logic Puzzle - Flip Flop
Logic Puzzle - Edge Detect
Logic Puzzle - Full Adder
Logic Puzzle - Padlock
Customisable Design - Padlock
Customisable Design - UART
Customisable Design - 7-Seg
Simple automated testing using truth tables
Generating Wokwi designs from truth tables
How do semiconductors work?
Introduction to SiliWiz
Draw a Resistor
Parasitics
Voltage Divider
Draw a capacitor
Draw an N MOSFET
Making a logic inverter
Draw a P type MOSFET
Draw a CMOS inverter
Making ASICs
Working with HDLs
Important!
FPGA to ASIC
HDL resources
HDL templates
Testing your design
Teaching resources
Tech specs
Clock
GPIO pins
Analog pins
Memory
Pinouts
PCB (TT04+)
PCB (TT02-03)
FAQ
Branding
Contact
Press
Terms
Credits
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Tiny Tapeout
>
Working with HDLs
> HDL templates
Verilog
HDL templates
Verilog
https://github.com/TinyTapeout/tt06-verilog-template
This repo shows how to:
specify the files
for building the ASIC
run an automatic test
when you push new code to the repo