You’ve used Wokwi or an HDL to make your digital design, but how do we go from there to an ASIC?
We use OpenLane, an open source tool that can convert a digital netlist in Verilog format to the GDS files needed for ASIC manufacture.
To make things easier, we install the tools and run them on GitHub’s servers. As the designs are open source, we get free computing power.
In this video I explain how it works and take a look at OpenLane and the logs produced.