Most FPGAs allow initial statements, and flops are often initialised to zero. This is not the case with ASICs, where flops will have a random initial value at power on. Initial statements are not allowed, so you must use an explicit reset.
In an FPGA, registers are ‘free’ in that every LUT has a flop. So people are used to doing lots of pipelining and registering. But in an ASIC, these are the most ’expensive’ cells in terms of area, so it’s better to do more with combinational and only use flops where necessary. This might mean doing deeper levels of combinational logic with fewer flops in between.
As well as functional testing with a simulator and testbench, you should consider gate level testing. This allows you to simulate the actual layout of your GDS (post synthesis).
You can find an example GitHub action workflow for gate level simulation here. This takes care of installing the models for the standard cells.