46 Neural dataflow fabric — bit-serial MAC cells on a self-routing switch :: Quicker, easier and cheaper to make your own chip!

How it works

This is a bit-serial neural dataflow fabric: signed multiply-accumulate cells sitting on a self-routing banyan switch, with a small processor beside them sharing the same 24 pins.

The fabric. An 8-port banyan network moves one bit per cycle. Ports are frozen by the D6 pin map: 0–3 are the MAC cells, 4 is edge-in, 5 is edge-out, 6 is a CPU-stub and 7 is spare. A packet is self-routing — its header names the destination and the switch elements read it as it passes, so nothing central schedules the traffic.

The frame. Time is divided into 14-cycle frames. Cycles 0–5 carry the header as three ACT/address pairs, most-significant bit first; cycles 6–13 carry the payload. sof (on uio_in[6]) realigns every counter in the design to frame zero, so a host that loses sync recovers by pulsing one pin. A realign truncates whatever frame is in flight — an in-progress memory transaction is restarted and a partial fetch loop is discarded — so it costs forward progress and is not a no-op.

What that means in practice, and the two cases differ:

One resync does not corrupt anything, but costs you the frame in flight. Swept one pulse per run across every arrival cycle of the reference program, the executed-instruction and completed-store counts are identical to no pulse at all.
Repeated resyncs cost measurable progress. Fourteen realigns in a single run leave the program one load and one store further behind over a fixed window.

Both are measurements of the same design; they differ in how many pulses the run contains, not in what a pulse does.

The computation. A 22-frame timetable drives a 2-2-1 schedule: three cells compute two hidden units and one output. Cells 0–2 carry the demo; cell 3 is clocked but idle, present so the array is uniform. Each cell accumulates a signed product bit-serially, with the sign handled on the final cycle of the frame. Three serialiser organs read the accumulators back out onto the fabric.

The processor beside it. (This paragraph was ladder-dependent and the ladder is now ruled: the 32-bit plane ships.) The top carries a 32-bit RV32I-subset core reaching memory off-chip through a byte-phase bus adapter. Every transaction is a whole 4-phase loop: the adapter drives one address byte per cycle on uo_out, takes one returned byte back on ui_in, and reports the transaction TYPE on uio_out[1:0] at phase 0 and the PHASE NUMBER at phases 1-3 — so the host learns what kind of transaction it is in the same sample it uses to stay aligned, at zero pin cost. A load costs two loops, a store three: address then data. The 32-bit plane occupies the same three pin groups the earlier 16-bit core used (ui_in, uo_out, uio_out[1:0]), which is why it needed no new pins. ⚠️ The core advances only when a transaction retires. That enable wire is a marked validation artifact rather than a ratified design decision, and this datasheet does not claim otherwise.

What is proved and what is not — stated precisely, because the distinction is the point of the project. Each MAC cell is generated from a Lean model proved correct in the Lean kernel, and the generated netlist is then proved equivalent to its arithmetic specification over all inputs by SAT. The signed accumulation is proved for the drive schedule the design specifies. The sequencer that produces that schedule, the pin wrapper, and the fabric glue are hand-written RTL and are not part of either proof. A layout of this composition measures area, timing, DRC, LVS and antenna — it is not a functional demo and not a proof of the whole.

How to test

Reset, then frame. Hold rst_n low, release it, then pulse sof on uio_in[6]. Every counter in the design returns to frame zero on that pulse — the sequencer, the fabric and the core's phase counter all read the same net, so they agree on where frame zero is.

That is a statement about alignment and not about safety, and the two were conflated in an earlier revision of this page. When a realign is harmless is a separate property: until the fetch_owed repair in busadapt8.v, asserting sof at a completed load or store's retiring edge, or during the first three cycles of the fetch loop that follows it, re-issued that completed transaction and destroyed the instruction being fetched. Four cycles per memory instruction; the fourth cycle of the fetch loop was already safe.

Measured on this design, sweeping one pulse per run across the steady-state window: 20 of 121 arrival cycles re-issued a completed store before the repair, 0 of 121 after. Over the whole run including bring-up the same comparison is 36 of 260 before, 0 of 260 after. (The 121- and 260-cycle windows are different populations and are given separately rather than as one improving ratio.)

The repair removes the defect by construction rather than by which cycle a pulse lands on: while a fetch is owed there is no resident instruction to re-derive from, so the only correct action is to fetch.

Drive an edge. Present serial data on uio_in[2] (edge_in_dat) with uio_in[3] as its valid. Results emerge on uio_out[4] (edge_out_dat) with uio_out[7] (valid) marking the cycles that carry them.

Watch the core. uio_out[1:0] reports the byte-phase; uo_out carries the address byte for that phase. Feeding instruction bytes back on ui_in in phase order walks the core through its loop.

Clock. The design is specified at a 55 ns period (18,181,818 Hz). That figure and clock_hz in the manifest are separate fields in separate files and nothing in either tool checks that they agree — they are kept equal by hand and by review.

⛔ THERE IS NO COCOTB BENCH IN THIS PROJECT YET, AND THIS SECTION DOES NOT PRETEND OTHERWISE — but it is no longer BLOCKED, only unwritten. It was blocked while the top was unruled: a testbench binds PROJECT_SOURCES, which must agree with source_files, which follows top_module, so a bench written against the wrong top is wasted twice. The ladder is now ruled, so the target is named and the bench is buildable. The manifest's source list is machine-checked against the RTL closure by docs/silicon-tools/manifest_check.sh, and assemble.sh REFUSES to build a submission tree while test/ is missing — so this gap cannot ship unnoticed.

Known limitation — one result per frame, and it is a design decision not a bug

The serialiser organs have no shift-enable: they shift on every load-low cycle. A 32-bit emission spread across four frames would therefore lose 24 bits into the header windows. This artifact emits one int8 frame per result instead. Full-width emission needs either a shift-enable port on the serialiser (about +32 selects) or per-frame reloads; it is priced and owed, and it does not move the area, timing, DRC, LVS or antenna numbers a layout of this composition produces.

Signoff — max-fanout DRV at the configuration this bundle submits

Written 2026-09-02 for the ndf-2a resubmission. It describes THIS configuration (branch ndf-2a, src/config.json) and no other; the 2026-08-19 submission it replaces carried no such note, deliberately — see the last paragraph.

What changed, and what did not. Four LibreLane keys differ from the 08-19 submission: PL_RESIZER_HOLD_SLACK_MARGIN 0.1 → 0.45, GRT_RESIZER_HOLD_SLACK_MARGIN 0.05 → 0.3, RSZ_CORNERS (resizing now against the four ss/tt corners instead of nom_tt alone), and CTS_SINK_CLUSTERING_SIZE = 10.

⚠️ AND THE RTL IS NO LONGER BYTE-IDENTICAL TO THE 08-19 SUBMISSION. This sentence said it was, and that was true until 2026-09-06. src/busadapt8.v now carries the fetch_owed repair: one flip-flop and one changed kind assignment, closing a window in which a host sof pulse re-issued a completed memory transaction and destroyed the instruction being fetched. That change is the reason every number in the table below moved. info.yaml, the pinout, the 55 ns clock and the 6x2 tile are unchanged.

What this configuration reports at signoff, all nine STA corners, fanout limit 10:

                              08-19 submission      this bundle
max_fanout violators                    117                3
   clock-tree leaves                    111                0
   datapath                               6                3     fanout 12, 12, 11
max_slew violators                     3317             1051
max_cap violators                        27               13
setup worst slack (55 ns period)   +5.668 ns        +8.023 ns
hold worst slack                   +0.111 ns        +0.190 ns
setup / hold TNS                       0 / 0            0 / 0
DRC · LVS · antenna                    0 / 0 / 0        0 / 0 / 0

The 08-19 column is the shuttle's own signoff for run 32284710003, reproduced locally bit-exactly (all 320 shared metrics identical) before the four keys were changed, so the delta is measured against the fabricated baseline and not against an approximation of it.

The three accepted violators, and why they are accepted. All three are resizer-inserted datapath buffers, at fanout 12, 12 and 11 against a limit of 10. None is a clock-tree leaf, verified from this bundle's own gate-level netlist: every load on all three is a combinational cell input, and no flop clock pin is driven by any of them. Their slack is absorbed: setup closes with +8.023 ns of margin on a 55 ns period and hold with +0.190 ns, TNS 0.0, in every corner — and setup slack improved at all nine corners against the 08-19 configuration. A datapath net one or two over the limit costs transition time on combinational paths that have that margin to spend. A clock-tree leaf over the limit is a different object — it lands on skew and insertion delay for every flop beneath it — which is why the 08-19 design's 111 clock-leaf violators were the thing worth fixing, and CTS_SINK_CLUSTERING_SIZE = 10 removes all 111.

The count changed with this bundle, and it is attributable. The 2026-08-28 council accepted at most one datapath violator at fanout 11–12, zero clock-leaf as the criterion for this configuration. This bundle reports three. Measured, not assumed: the previous configuration's RTL re-hardened under this bundle's own toolchain reproduces its earlier signoff on all 322 metrics, so the increase is caused by the fetch_owed repair in busadapt8.v and not by the build environment. The repair's own net is fanout 1; the additional violators are a placement consequence of one added flip-flop, not a fanout its logic demands. On 2026-09-06 the count clause was amended to at most three datapath violators in the 11–12 band, zero clock-leaf unchanged, and this bundle meets the amended criterion. The provenance of that amendment, recorded because a signoff criterion changed without one is worth less than the criterion it replaces: the Captain ruled "ship (B)" on 2026-09-06 and that ruling covered the ship only; the count clause was not put to him, and it took the helm's stated default-if-silent, which was the lead's own recommendation. The zero-clock-leaf clause was neither amended nor at issue — and it is the clause this section calls the serious one.

Why the previous bundle carried no such note. The 08-19 submission documents the design as fabricated, in which none of these three violators exists and the fanout count is 117. A note naming three accepted violators would have told a reader that the fabricated part has three; it has 117. Artifact and evidence describe the same chip at the same time, or they do not travel together — so this note ships with the configuration it measures, and not before.

External hardware

None. The design needs no external hardware: drive the pins directly, or from a microcontroller if you want to stream frames faster than by hand.

#	Input	Output	Bidirectional
0	instr_byte[0] — CPU memory bus	addr_byte[0] — PC bytes, 4 phases	phase_o[0] (out): phase strobe
1	instr_byte[1] — CPU memory bus	addr_byte[1] — PC bytes, 4 phases	phase_o[1] (out): phase strobe
2	instr_byte[2] — CPU memory bus	addr_byte[2] — PC bytes, 4 phases	edge_in_data (in): packet port, weights/inputs
3	instr_byte[3] — CPU memory bus	addr_byte[3] — PC bytes, 4 phases	edge_in_valid (in): packet port, weights/inputs
4	instr_byte[4] — CPU memory bus	addr_byte[4] — PC bytes, 4 phases	edge_out_data (out): packet port, results
5	instr_byte[5] — CPU memory bus	addr_byte[5] — PC bytes, 4 phases	edge_out_valid (out): packet port, results
6	instr_byte[6] — CPU memory bus	addr_byte[6] — PC bytes, 4 phases	sof (in): non-destructive frame re-align; rst_n is DESTRUCTIVE once the die carries state
7	instr_byte[7] — CPU memory bus	addr_byte[7] — PC bytes, 4 phases	valid (out): payload-window flag; phase recovers from its rising edge, which uniquely names cycle 6 of a 14-cycle frame

46 Neural dataflow fabric — bit-serial MAC cells on a self-routing switch