839 Darga CiROM digital read + ternary MAC
839 : Darga CiROM digital read + ternary MAC
- Author: mpai17
- Description: Mask-programmed ternary compute-in-ROM read fully digitally: clocked bitline sampling of a 64x32 1T NOR array plus an on-die ternary MAC, no comparators, no VREF, no analog pins
- GitHub repository
- Open in 3D viewer
- Open in Tiny Tapeout Explorer
- Clock: 20000000 Hz
How it works
Darga reads a mask-programmed ternary compute-in-ROM array fully digitally and computes matrix-vector products on die. Ternary weights (+1 / -1 / 0) are baked into a 64x32 1T NOR array: a cell places a discharge transistor on a column's BLP line for +1, on its BLN line for -1, or on neither for 0. The baked pattern is the seeded sparse test0 matrix, the same mask program as the Azara CiROM analog tile on this shuttle: the two tiles are a controlled experiment in readout style, identical array and weights, analog comparator sense versus this tile's digital sampling.
To read a row the controller precharges all 64 bitlines high, asserts the one-hot wordline so the programmed cells discharge their bitlines, waits a configured strobe delay, then samples every bitline into a standard-cell flop. A discharged BLP reads +1, a discharged BLN reads -1, neither reads 0. There is no comparator, no reference voltage, and no analog pin: full-swing sampling replaces the entire sense subsystem.
On top of the readout sits an on-die ternary MAC: the host streams a 64-element vector of 4-bit activation magnitudes, and for each row the sampled weight sign adds, subtracts, or skips the activation in 12-bit accumulators (4 accumulators covering the 32 columns in 8 passes). This is the first vehicle in the Ankhdjet series that computes dot products on silicon.
How to test
- Reset (
rst_nlow, then high). Optionally shift a 16-bit config word in onuio_in[4](cfg_in) withuio_in[3](cfg_mode) high: bits [3:0] strobe delay, [7:4] precharge width, [8] precharge bypass; reset defaults are the fastest timing. - Matrix-vector multiply (
uio_in[2]= 0): pulseuio_in[1](start), then stream the activation vector one byte per row pair onui_inwithuio_in[0](act_wr) high, low nibble = even row; the vector is re-sent for each of the 8 column-group passes, and the controller stalls when starved, so any slower host is safe. After each pass, watchuio_out[5](result_valid): the pass's 4 accumulators stream onuo_outas 2 bytes each, low byte first, 64 result bytes total in ascending column order.uio_out[7](done) marks the end. - Raw row read (
uio_in[2]= 1): drive the row address onui_in[5:0]and pulse start; 8 bytes of{neg_hit, pos_hit}stream out, reproducing the analog tile's readout on the shared 16 columns and extending it to all 32. - Check results against the golden model: every row's expected weights are the corresponding line of
weights/test0.wmatin the Ankhdjet repo, and an MVM's expected value is that matrix times the streamed vector. Sweep the clock to map the read-timing margin.
External hardware
None: the tile is fully digital. A microcontroller or the demo board streams activations and compares results against the golden model.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | act byte [0] / row_addr[0] | result[0] | act_wr (in) |
| 1 | act byte [1] / row_addr[1] | result[1] | start (in) |
| 2 | act byte [2] / row_addr[2] | result[2] | mode (in): 0=MVM, 1=raw row read |
| 3 | act byte [3] / row_addr[3] | result[3] | cfg_mode (in) |
| 4 | act byte [4] / row_addr[4] | result[4] | cfg_in (in) |
| 5 | act byte [5] / row_addr[5] | result[5] | result_valid (out) |
| 6 | act byte [6] | result[6] | busy (out) |
| 7 | act byte [7] | result[7] | done (out) |