933 Smartcard PLL Clock Generator
933 : Smartcard PLL Clock Generator
- Author: William Anthony
- Description: Enable-controlled PLL clock generator model for smartcard timing experiments
- GitHub repository
- Open in 3D viewer
- Clock: 13560000 Hz
How it works
This project exposes an enable-controlled smartcard PLL model through the Tiny Tapeout interface.
- The Tiny Tapeout
clkpin is used as the PLL reference input. ui[0]is the PLL enable control. Whenui[0]=1andena=1, the PLL logic runs.ui[7:4]configures divider ratio for the feedback path.uio[3:0]configures charge pump gain.- The main output and divided clocks are exported on
uo[4],uo[3], anduo[2]. - Lock status is exported on
uo[0]anduo[1].
Operational intent:
- Turn ON by asserting
ena=1, releasing reset (rst_n=1), and settingui[0]=1. - Turn OFF by setting
ui[0]=0(intentional disable). - After disable, clock outputs are expected to stop and lock status should drop.
How to test
- Go to the
testfolder. - Run RTL simulation:
make -B
- The cocotb test checks three key behaviors:
- PLL output does not toggle while disabled.
- PLL output toggles after explicit enable.
- PLL output stops again after explicit disable.
You can inspect waveforms using GTKWave:
gtkwave tb.fst tb.gtkw
External hardware
No external hardware is required for RTL verification.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | PLL enable | Lock detect | CP gain bit 0 (input) |
| 1 | Reserved | Almost lock | CP gain bit 1 (input) |
| 2 | Reserved | CLK/4 output | CP gain bit 2 (input) |
| 3 | Reserved | CLK/2 output | CP gain bit 3 (input) |
| 4 | Divider ratio bit 0 | PLL output clock | VCO monitor bit 0 (output) |
| 5 | Divider ratio bit 1 | PFD up monitor | VCO monitor bit 1 (output) |
| 6 | Divider ratio bit 2 | PFD down monitor | VCO monitor bit 2 (output) |
| 7 | Divider ratio bit 3 | Active enable status | VCO monitor bit 3 (output) |