143 FFD16 cpu 16-bit

143 : FFD16 cpu 16-bit

Design render

Remedy CPU / TinyCPU Datasheet

How to test

Use the custom IDE/toolchain to assemble TinyCPU assembly, or the work-in-progress cpp-ish compiler, then upload the generated program image to the external flash. I am also working on a vscode extension to integrate these steps into a more user-friendly workflow. with code upload, flash programming, and serial debugging features hopefully.

Here is the Repo link : https://github.com/leonidas213/Remedy-Compiler

Assembler

image

Work in progress compiler

image

External hardware

The CPU uses external serial memory instead of internal program/data memory.

Device Mode used by current hardware Purpose
SPI/QSPI Flash QSPI continuous-read mode Program fetch and ldf flash reads
SPI RAM / PSRAM Plain SPI mode Data load/store

The CPU is a 16-bit design and only reads/writes memory in 16-bit half-words. CPU memory addresses are word addresses. Externally, the memory interface appends one zero bit to form byte addresses, so CPU address 0x0001 maps to external byte address 0x000002.

Usable external address range:

CPU word address: 0x0000-0xFFFF
External byte address used: 0x00000-0x1FFFF
Effective byte range: 128 KiB per memory device

Example: if flash byte memory starts with 0x3D F1 25 48, the CPU can read 0x3DF1 at word address 0x0000 and 0x2548 at word address 0x0001. It cannot directly read the unaligned half-word 0xF125.

Pin usage

Pin group Use
ui_in[5:0] General input pins
ui_in[6] Debug serial data input
ui_in[7] Debug serial clock input
uo_out[5:0] General output pins from OutputReg[5:0]
uo_out[6] General output OutputReg[6], or I2C SCL when I2C is active
uo_out[7] General output OutputReg[7], or debugger data output when debugger drives it
uio[0] Flash CS
uio[1] Flash/RAM IO0 / MOSI
uio[2] Flash/RAM IO1 / MISO
uio[3] Shared serial clock
uio[4] Flash IO2
uio[5] Flash IO3
uio[6] RAM CS
uio[7] I2C SDA

Memory interface

Startup flash initialization

At reset the memory interface initializes the flash before the CPU can fetch instructions. The current startup sequence is:

0x66              ; flash reset enable
0x99              ; flash reset
0x06              ; write enable
0x31 0x02         ; set status/config register 2, enable quad mode
0xEB              ; enter QSPI fast-read/continuous-read path
0x00 0x00 0x00 0xA0 0x00 0x00
                  ; address 0, mode bits A0, dummy clocks

RAM reset/init was removed to save area. RAM CS stays high during flash initialization.

Runtime flash read

Flash is treated as read-only by this memory interface. Runtime flash access uses QSPI continuous read:

CS low
24-bit byte address = {7'b0, cpu_addr[15:0], 1'b0}
2 QSPI mode nibbles: A, 0
4 QSPI dummy clocks
4 QSPI data clocks = 16-bit word
CS high

The external SPI/QSPI clock toggles every system clock, so one external serial clock period is two system clock cycles.

Runtime RAM read/write

RAM uses normal SPI:

Read command  = 0x03
Write command = 0x02
24-bit byte address = {1'b0, 6'b0, cpu_addr[15:0], 1'b0}
16-bit data word

Flash writes are intentionally blocked in the current memory wrapper.

CPU specs

image

Overview

  • 16-bit CPU datapath
  • 16 general purpose 16-bit registers
  • r13/BP, r14/SP, and r15/RA are conventionally used as branch pointer, stack pointer, and return address, but they are still can be used as normal registers
  • 16-bit instruction words
  • Immediate words have MSB = 1 and load the immediate register instead of executing as a normal opcode
  • External flash and RAM are accessed only as 16-bit half-words
  • ALU flags: Negative, Zero, Carry
  • Fixed interrupt vector: 0x0002
  • Debugger supports halt/run/step, one dynamic breakpoint, static brk, and jump/load-PC

Immediate format

Any fetched word with bit 15 set is treated as an immediate word. It updates the immediate register and does not execute as a normal instruction. The following real instruction can then consume that immediate value.

Example concept:

; Assembly:
jump 0xF123

; Encoded as two 16-bit words:
0xF123     ; immediate word
0x3C01     ; absolute jump instruction using the immediate register/sign bit field

This is why the debugger can also inject multi-word commands by feeding the same 16-bit words the flash would have returned.

Timers

There are two timers:

Timer Counter width Target width Read address
Timer 1 16-bit 16-bit timer1ReadAdr = 5
Timer 2 9-bit 9-bit timer2ReadAdr = 9

Timer 2 is called the tiny timer in the RTL, but it is currently 9-bit, not 8-bit.

Both timers use the same 8-bit config layout:

Bit(s) Name Meaning
[0] enable Enables the timer
[4:1] prescaler Prescaler select
[5] auto reload When target matches, reset count to zero instead of staying at target
[6] IRQ enable Timer asserts interrupt when target matches

Prescaler encoding:

Value Divide
0 /1
1 /2
2 /4
3 /8
4 /16
5 /32
6 /64
7 /128
8 /256
9 /512
10 /1024
11 /2048
12-15 reserved/currently behaves like /1

Examples:

Source Prescaler Timer tick
System clock /2048 81.92 us

Max overflow times with /2048:

Timer System clock source
16-bit timer about 5.37 s
9-bit timer about 41.94 ms

Notes:

  • A target value of zero disables match detection because the RTL uses target != 0 as target_valid.
  • During interrupt lock (InterLock), the timer count does not advance. The prescaler can still advance when the timer is enabled.
  • Writing to the timer reset address with bit 0 set clears count, clears prescaler, and clears timer config.
  • Writing timerSyncStart updates bit 0, the enable bit, of both timer configs at the same time.

Interrupts

The interrupt system uses one fixed interrupt vector and software dispatch:

Interrupt vector = 0x0002
Return instruction = reti

Interrupt sources:

Bit Source
0 Timer 1
1 Timer 2
2 I2C

There is no separate per-input-pin interrupt source in the current top-level wiring.

Interrupt registers:

Address Name Write behavior Read behavior
13 CpuinterruptEnable bit 0 = global interrupt enable bit 0 = global enable, bit 1 = IRQ lock, bit 2 = active interrupt request
14 InputInterruptEnable bits [2:0] = IRQ source enable mask current IRQ enable mask
15 InterruptRegister write 1s to clear pending bits current pending bits

Important behavior:

  • IRQ requests are latched into pending bits.
  • InterruptRegister is write-one-to-clear.
  • Interrupts are blocked while imm is active, so an interrupt should not break an immediate word plus the following immediate-consuming instruction.
  • Once an interrupt is taken, the controller locks until reti is executed.
  • If another source becomes pending while locked, it remains pending and can trigger after reti if still enabled.

A typical ISR should read InterruptRegister, handle each set bit, clear the handled bits by writing 1s back to InterruptRegister, then execute reti.

I2C master

The I2C block is now a small fixed-speed master. It does not use the old programmable 16-bit prescaler anymore.

Approximate SCL rate:

SCL ≈ clk / (3 * (I2C_DIV + 1))
I2C_DIV = 20
At 25 MHz: SCL ≈ 397 kHz

I2C register map:

CPU address Lower I2C reg Name Description
16 0 I2cCtrl bit 0 = enable, bit 1 = IRQ enable
17 1 I2cStatus bit 0 busy, bit 1 bus active, bit 2 done, bit 3 ack error, bit 4 rx valid, bit 5 interrupt pending/done
18 2 I2cDivider / legacy I2cPrescaler read-only divider value, currently 20
19 3 I2cDataReg write TX byte / read RX byte
20 4 I2cCommand command bits

I2cStatus sticky bits are cleared by writing 1s:

Status bit Clear behavior
2 write 1 to clear done
3 write 1 to clear ack_error
4 write 1 to clear rx_valid

Command register bits:

Bit Command
0 START
1 STOP
2 WRITE byte
3 READ byte
4 NACK after read

You can combine bits, for example START+WRITE for address phase, READ+NACK+STOP for the final byte of a read transaction.

Debugger

The debug serial frontend receives 32-bit frames using the debug clock and debug data input:

8'hA5 sync + 4-bit command + 4-bit register address + 16-bit data

Commands:

Command Meaning
0 Ping
1 Read debug register
2 Write debug register

Responses are 16-bit:

Response Meaning
0xDB12 Ping response
0xACCE Write accepted
read data Read command response
0xEEEE Invalid/error response

Debug registers:

Reg Name Description
0 ID reads 0xDB11
1 STATUS bit 0 halt request, bit 1 jump pending, bit 3 halted, bit 4 debug enable, bit 5 static break enable, bit 6 breakpoint enable, bit 7 resume mask
2 CONTROL bit 0 debug enable, bit 1 halt request, bit 2 run pulse, bit 3 step pulse, bit 5 static break enable, bit 6 jump/load-PC request
3 FLAGS bit 0 Negative, bit 1 Zero, bit 2 Carry
4 PC current program counter
5 IR current instruction register
6 BP0 dynamic breakpoint address
7 BPCTRL bit 0 enables BP0
8 JUMP_ADDR address used by CONTROL bit 6

Only one dynamic breakpoint is currently implemented. The static breakpoint instruction is opcode 0x49 / brk; it only halts when static break is enabled.

Register map

InputReg               = 0    ; 16-bit read, lower 8 bits contain input pins/debug pins
OutputReg              = 1    ; 8-bit output register

timer1Config           = 2    ; 8-bit timer config
timer1Target           = 3    ; 16-bit target
timer1Reset            = 4    ; write bit 0 = reset timer1
timer1ReadAdr          = 5    ; read 16-bit timer1 count

timer2Config           = 6    ; 8-bit timer config
timer2Target           = 7    ; 9-bit target
timer2Reset            = 8    ; write bit 0 = reset timer2
timer2ReadAdr          = 9    ; read 9-bit timer2 count, zero-extended

timerSyncStart         = 10   ; write bit 0 to update enable bit of both timers

RandomSeedAddr         = 11   ; write 8-bit RNG seed
RandomReg              = 12   ; read generated random value

CpuinterruptEnable     = 13   ; global interrupt control/status
InputInterruptEnable   = 14   ; IRQ source enable mask, legacy name
InterruptRegister      = 15   ; IRQ pending register, write-one-to-clear

I2cCtrl                = 16
I2cStatus              = 17
I2cDivider             = 18   ; fixed divider readback, legacy name I2cPrescaler
I2cDataReg             = 19
I2cCommand             = 20

Programming examples

Basic addition and store
ldi r1, 0x12
ldi r2, 0x20
add r1, r2
st 0x1000, r1
putoutput r1
Timer 1, system-clock source, /2048, IRQ enabled, auto reload enabled

Config value:

irq=1, reload=1, prescaler=11, enable=1
config = (1<<6) | (1<<5) | (11<<1) | 1 = 0x77

ldi r1, 0x77
out timer1Config, r1
ldi r1, 1000
out timer1Target, r1
Timer 2, /2048, IRQ enabled, auto reload enabled

Config value:

irq=1, reload=1, prescaler=11, enable=1
config = (1<<6) | (1<<5) | (11<<1) | 1 = 0xF7

ldi r1, 0xF7
out timer2Config, r1
ldi r1, 511
out timer2Target, r1
Interrupt handler skeleton
jump main
nop
interrupt_handler: ;at memory address 0x0002
    in r0, InterruptRegister

    ; timer1 pending?
    mov r1, r0
    and r1, 1
    jumpZero check_timer2
    ; handle timer1 here
    ldi r1, 1
    out InterruptRegister, r1

check_timer2:
    mov r1, r0
    and r1, 2
    jumpZero check_i2c
    ; handle timer2 here
    ldi r1, 2
    out InterruptRegister, r1

check_i2c:
    mov r1, r0
    and r1, 4
    jumpZero irq_done
    ; handle i2c here
    ldi r1, 4
    out InterruptRegister, r1

irq_done:
    reti

main:
    ; main program here
    jump main

Opcode Table

Opcode Instruction Description
0x00 nop Does nothing.
0x01 mov rd, rs Move the content of Rs to register Rd
0x02 add rd, rs Adds the content of register Rs to register Rd without carry.
0x03 adc rd, rs Adds the content of register Rs to register Rd with carry.
0x04 sub rd, rs Subtracts the content of register Rs from register Rd without carry.
0x05 sbc rd, rs Subtracts the content of register Rs from register Rd with carry.
0x06 and rd, rs Performs a bitwise AND between Rd and Rs, and stores the result in Rd.
0x07 or rd, rs Performs a bitwise OR between Rd and Rs, and stores the result in Rd.
0x08 xor rd, rs Performs a bitwise XOR between Rd and Rs, and stores the result in Rd.
0x09 ldi rd, i16 Loads Register Rd with the constant value [value].
0x0A ldi rd, u4 Loads Register Rd with the constant value [value].
0x0B add rd, i16 Adds an immediate constant [value] to register Rd without carry.
0x0C add rd, u4 Adds an immediate constant [value] to register Rd without carry.
0x0D adc rd, i16 Adds an immediate constant [value] to register Rd with carry.
0x0E adc rd, u4 Adds an immediate constant [value] to register Rd with carry.
0x0F sub rd, i16 Subtracts an immediate constant [value] from register Rd without carry.
0x10 sub rd, u4 Subtracts an immediate constant [value] from register Rd without carry.
0x11 sbc rd, i16 Subtracts an immediate constant [value] from register Rd with carry.
0x12 sbc rd, u4 Subtracts an immediate constant [value] from register Rd with carry.
0x13 neg rd Stores the two's complement of Rd in register Rd.
0x14 and rd, i16 Performs a bitwise AND between Rd and an immediate constant [value], and stores the result in Rd.
0x15 and rd, u4 Performs a bitwise AND between Rd and an immediate constant [value], and stores the result in Rd.
0x16 or rd, i16 Performs a bitwise OR between Rd and an immediate constant [value], and stores the result in Rd.
0x17 or rd, u4 Performs a bitwise OR between Rd and an immediate constant [value], and stores the result in Rd.
0x18 xor rd, i16 Performs a bitwise XOR between Rd and an immediate constant [value], and stores the result in Rd.
0x19 xor rd, u4 Performs a bitwise XOR between Rd and an immediate constant [value], and stores the result in Rd.
0x1A not rd Stores not Rd in register Rd.
0x1B reserved
0x1C reserved
0x1D reserved
0x1E cmp rd, rs Compares Rd, and Rs (subtracts Rs from Rd without storing the result) Without using carry flag. Flags are updated accordingly.
0x1F cpc rd, rs Compares Rd, and Rs (subtracts Rs from Rd without storing the result) With carry flag. Flags are updated accordingly.
0x20 cmp rd, i16 Compares Rd, and an immediate constant [value] (subtracts Rs from Rd without storing the result) Without using carry flag. Flags are updated accordingly.
0x21 cmp rd, u4 Compares Rd, and an immediate constant [value] (subtracts Rs from Rd without storing the result) Without using carry flag. Flags are updated accordingly.
0x22 cpc rd, i16 Compares Rd, and an immediate constant [value] (subtracts Rs from Rd without storing the result) With carry flag. Flags are updated accordingly.
0x23 cpc rd, u4 Compares Rd, and an immediate constant [value] (subtracts Rs from Rd without storing the result) With carry flag. Flags are updated accordingly.
0x24 lsl rd Shifts register Rd by one bit to the left. A zero bit is filled in and the highest bit is moved to the carry bit.
0x25 lsr rd Shifts register Rd by one bit to the right. A zero bit is filled in and the lowest bit is moved to the carry bit.
0x26 rol rd Shifts register Rd by one bit to the left. The carry bit is filled in and the highest bit is moved to the carry bit.
0x27 ror rd Shifts register Rd by one bit to the right. The carry bit is filled in and the lowest bit is moved to the carry bit.
0x28 asr rd Shifts register Rd by one bit to the right. The MSB remains unchanged and the lowest bit is moved to the carry bit.
0x29 swap rd Swaps the high and low byte in register Rd.
0x2A swapn rd Swaps the high and low nibbles of both bytes in register Rd.
0x2B st [rd], rs Stores the content of register Rs to the memory at the address [Rd] from Ram.
0x2C ld rd, [rs] Loads the value at memory address [Rs] to register Rd from Ram.
0x2D st i16, rd Stores the content of register Rs to memory at the location given by [const] from Ram.
0x2E st u4, rd Stores the content of register Rs to memory at the location given by [const] from Ram.
0x2F ld rd, i16 Loads the memory value at the location given by [const] to register Rd from Ram.
0x30 ld rd, u4 Loads the memory value at the location given by [const] to register Rd from Ram.
0x31 st [rd +- value], rs Stores the content of register Rs to the memory at the address (Rd+[const]) from Ram.
0x32 ld rd, [rs +- value] Loads the value at memory address (Rs+[const]) to register Rd from Ram.
0x33 Reserved
0x34 jumpCarry i8 Jump if Carry flag is set. (Relative, max jump +-128).
0x35 jumpZero i8 Jump if Zero flag is set. (Relative, max jump +-128).
0x36 jumpNegative i8 Jump if Negative flag is set. (Relative, max jump +-128).
0x37 jumpNotCarry i8 Jump if Carry flag is not set. Relative jump.
0x38 jumpNotZero i8 Jump if Zero flag is not set. Relative jump.
0x39 jumpNotNegative i8 Jump if Negative flag is not set. Relative jump.
0x3A rcall rd, i16 store current value to the Rd register and jump to immediate value.
0x3B rret rs Return/jump to the address stored in register Rs.
0x3C jump i16 absolute Jump to memory address.
0x3D jump i8 Relative jump using signed offset. Assembler chooses this when possible.
0x3E out i16, rs writes Rd register value to the immediate address.
0x3F out u4, rs writes Rd register value to the immediate address.
0x40 outr [rd], rs writes Rd value to the adress in the Rs register.
0x41 in rd, i16 Reads the value at immediate address into Rd.
0x42 in rd, u4 Reads the value at immediate address into Rd.
0x43 inr rd, [rs] Reads the value at Rs value address into Rd.
0x44 reti Only used in interrupt function. it will return to the address when the interrupt happened.
0x45 ldf rd, [rs] Reads the value at Rs value address into Rd from flash memory.
0x46 ldf rd, i16 Reads the immediate address into Rd from flash memory.
0x47 ldf rd, u4 Reads the immediate address into Rd from flash memory.
0x48 ldf rd, [rs +- value] Loads the value at memory address (Rs+-[const]) to register Rd from flash memory.
0x49 brk Static breakpoint instruction. Only halts when debugger static break is enabled.

IO

#InputOutputBidirectional
0cpu input pin [0]cpu output pin [0]spi_flash_cs
1cpu input pin [1]cpu output pin [1]spi_miso/Qdio[0]
2cpu input pin [2]cpu output pin [2]spi_mosi/Qdio[1]
3cpu input pin [3]cpu output pin [3]spi_sclk
4cpu input pin [4]cpu output pin [4]Qdio[2]
5cpu input pin [5]cpu output pin [5]Qdio[3]
6cpu input pin [6] / Debug clockcpu output pin [6] / I2c_sclspi_ram_cs
7cpu input pin [7] / Debug Data Incpu output pin [7] / Debug Data OutI2c_sda

Chip location

Controller Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Analog Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Analog Mux Mux Mux Mux Analog Mux Mux Mux Mux Mux Mux tt_um_chip_rom (Chip ROM) tt_um_factory_test (Tiny Tapeout Factory Test) tt_um_oscillating_bones (Oscillating Bones) tt_um_wokwi_457142813149930497 (TinyTapeOut workshop) tt_um_wokwi_457311688017142785 (tiny tapeout test gates) tt_um_bfcpu (bfCPU) tt_um_rebeccargb_universal_decoder (Universal Binary to Segment Decoder) tt_um_rebeccargb_hardware_utf8 (Hardware UTF Encoder/Decoder) tt_um_rebeccargb_intercal_alu (INTERCAL ALU) tt_um_rebeccargb_vga_pride (VGA Pride) tt_um_wokwi_457215959798165505 (4-bit N frequency divider) tt_um_ppu_aebarthyi (simple_ppu) tt_um_riscyv02 (RISCY-V02) tt_um_pong (Pong) tt_um_LH_TapeoutMultiplier (tt_um_LH_TapeoutMultiplier) tt_um_wokwi_457571222315471873 (7 Seg C) tt_um_wokwi_457571216758012929 (Mikes Second) tt_um_wokwi_457569452934172673 (FirstTinyTapeoutWokwiProject) tt_um_wokwi_457571159626309633 (Tiny Tapeout V1) tt_um_wokwi_457577038845586433 (TinyTapeOut) tt_um_wokwi_457571280506256385 (Tiny tapeouts test gates) tt_um_wokwi_457576742418338817 (calculator) tt_um_wokwi_457571219715001345 (Ami's TT Logic Gates) tt_um_wokwi_457571067547656193 (Mikes First Wokwi design) tt_um_wokwi_457571453314827265 (Tiny tapeout one hot to seven segment display 1-8) tt_um_wokwi_457572218833202177 (4bit adder and hex converter) tt_um_wokwi_463741407580251137 (Lady's First Tapeout) tt_um_wokwi_457571138696714241 (jdisplayer) tt_um_wokwi_457570687900145665 (Tiny Tapeout Test Gates) tt_um_wokwi_457577511431565313 (Tiny Tapeout Test Gates) tt_um_wokwi_457571262875481089 (Tiny Tapeout) tt_um_wokwi_457571417674762241 (TamTries Tiny Tapeout) tt_um_wokwi_457571366985520129 (georgies wokwi design) tt_um_wokwi_457571701752981505 (WilfTT) tt_um_wokwi_457572875733692417 (First WOKWI Design) tt_um_wokwi_457571571887847425 (tiny tapeout gate test) tt_um_wokwi_457571352249873409 (First Wokwi design) tt_um_wokwi_457571405919170561 (Namo's first tapeout) tt_um_wokwi_457571339952163841 (OR Gate with NAND) tt_um_wokwi_457571188658258945 (Abishag's first Wokwi Design) tt_um_wokwi_457571426719781889 (Tiny) tt_um_wokwi_457571268900604929 (tiny tape GDS) tt_um_wokwi_457571949070179329 (Tom Haley Tiny Tape Out Design ) tt_um_alex_ha_192 (alex_ha_192) tt_um_wokwi_457577241913913345 (tiny tapeout test gates ) tt_um_wokwi_457571297367365633 (First Wokwi Attempt) tt_um_wokwi_457571363309211649 (idk yet) tt_um_wokwi_457571305740256257 (Work In progress title) tt_um_wokwi_457579594627462145 (TinyTapeoutProjectDefne) tt_um_wokwi_457571274041781249 (Tiny Tapeout Workshop by Kirsty Tan) tt_um_wokwi_457571233499594753 (Tiny Tapeout Workshop) tt_um_wokwi_457570205537212417 (Tiny Tapeout Test Project) tt_um_ojas_sharma_imperial_ttcpu (ttcpu 4-bit RISC microprocessor) tt_um_wokwi_457571271419289601 (chip one) tt_um_wokwi_457573490746716161 (Name Serial Printer) tt_um_wokwi_457569507958215681 (Tiny tapeout proj) tt_um_wokwi_457577929607958529 (Random 1st Attempt) tt_um_wokwi_457571438667259905 (PD+PFD+FreqDiv) tt_um_wokwi_457571602706552833 (Joe's first Wokwi design) tt_um_wokwi_457571471659666433 (Nicolas' first Wokwi design) tt_um_wokwi_457571148733696001 (Tiny Tapeout Workshop 1) tt_um_wokwi_457572520479222785 (Tiny Tapeout: Buenos días Mundo! ) tt_um_wokwi_457571494688497665 (First Chip) tt_um_wokwi_457571341266031617 (D-Type Flip Flop) tt_um_wokwi_457581344351934465 (WOKWI) tt_um_wokwi_457571462196267009 (Tiny Tapeout) tt_um_wokwi_457571359410603009 (TinyTapeout) tt_um_Terdoo_Osu (Spiking Pattern Recognition Core) tt_um_wokwi_457571319408448513 (Mani TinyTapeout) tt_um_wokwi_457571298662360065 (Tiny Tapeout Test Gates) tt_um_wokwi_457573015156590593 (Lil tapeout) tt_um_wokwi_457576363047649281 (Inverter) tt_um_wokwi_457571216488527873 (Tiny Tapeout Template Copy Paul 1) tt_um_wokwi_457571472208072705 (Tiny Tapeout Test design) tt_um_wokwi_457571381968631809 (Tiny tapeout test) tt_um_wokwi_457571314694049793 (Tiny Tapeout Test) tt_um_wokwi_457571368009979905 (Tiny Tapeout Test Gates) tt_um_wokwi_457571389542502401 (First thing) tt_um_wokwi_457570267471381505 (Tiny Tapeout) tt_um_wokwi_457571563051492353 (CS First Wokwi design) tt_um_wokwi_457577392775721985 ( tiny Tapeout Test Gate) tt_um_wokwi_457570279596067841 (Tiny Tapeout Workshop - AJJ) tt_um_wokwi_457571180646081537 (Alins Password) tt_um_wokwi_457572360568198145 (Tiny Tapeout) tt_um_wokwi_457571270578328577 (Tiny tapeout workshop) tt_um_wokwi_457581625098771457 (Tiny Tapeout First Test Run) tt_um_wokwi_442342513281875969 (First Design) tt_um_wokwi_457581848269362177 (Tiny Tapeout Brainf*ck?) tt_um_sap_alexanderholden (sap1) tt_um_wokwi_457571752214675457 (3bit_ALU) tt_um_wokwi_457571542558115841 (Tiny Tapeout") tt_um_wokwi_457573095390500865 (Tiny Tapeout Workshop Counter) tt_um_wokwi_457571511812802561 (Akash's first Wokwi design) tt_um_wokwi_457577563633889281 (Tiny Tapeouts gate tests) tt_um_wokwi_457576950671858689 (Hymns_GDS) tt_um_wokwi_457571371384299521 (Digital digit display circuit - TINYTAPEOUT) tt_um_rowantylerr_RC_TDC (Resistor Capacitor TDC) tt_um_wokwi_463662181299058689 (2 bit ALU) tt_um_chinghey (Hey FlexCompute-130) tt_um_8b10 (serdes8b10) tt_um_rom_vga_screensaver (VGA Screensaver with embedded bitmap ROM) tt_um_mayamelon_top (Tiny PI Controller) tt_um_JAIMEPRYOR0_VGA_YAY (VGA_YAY) tt_um_2048_vga_game (2048 sliding tile puzzle game (VGA)) tt_um_mng2_2ncos (A Tale of Two NCOs) tt_um_shimmydee_checkers (One-tile ADC) tt_um_urish_simon (Simon Says memory game) tt_um_dheeeraaj_sine_chirp_beacon (DDS Sine Chirp Beacon) tt_um_nicholas_ls194a (Universal Shift Register (SN74LS194A compatible)) tt_um_BellaB05_Hearts (Pink Hearts) tt_um_scottshuynh_ad_astra (ASIC Ad Astra) tt_um_liamolucko_vga (VGA demo) tt_um_lledoux_s3fdp_seqcomb (S3FDP Seq+Comb Stream Core) tt_um_5482582_cat_vga (Cat VGA) tt_um_vga_example_directional_toggle (Directional toggle of VGA playground example) tt_um_jimbok_ro_puf (Ring Oscillator PUF) tt_um_xxsahanaxx_hwsec_glitch (Hardware Security Glitching Attack) tt_um_NguyenHuuHenry_vga_project (VGA_Project) tt_um_irfantekin_analog (tt_um_irfantekin_analog) tt_um_chicagojones_sky26a_trng (Sky26a Advanced TRNG) tt_um_yen (YEN) tt_um_pedometer (Ultra Low Power Pedometer ASIC) tt_um_analog_atenfyr1 (Configurable Self-biasing Miller-compensated OTA) tt_um_aes_sbox (Formally-Verified Constant-Time AES S-Box) tt_um_tcpu_alienflip (tcpu) tt_um_nebula (Sierpinski Fractal Starfield) tt_um_zenith_tx26 (Zenith TX26) tt_um_odgrip_demoscene_ttsky26a (My first demoscene) tt_um_vighnesh_sawant_plane (Plane with a banner) tt_um_glyph_mode_hd (Glyph Mode HD) tt_um_TSARKA_TinyQV (TinyQV Wishbone SoC) tt_um_SimpleCounter (Simple Counter) tt_um_cfar_nobuzzer (CFAR Detector without Buzzer) tt_um_present (Present) tt_um_top (Approximate Logic Unit) tt_um_goose (OIIA-goose) tt_um_riscv_core (Tiny RISC-V) tt_um_dac_test3v3 (Design and Implementation of R-2R Ladder DAC for GPR Application) tt_um_tadc_its (Time Domain ADC) tt_um_algofoogle_vga_matrix_dac (Analog VGA CSDAC experiments) tt_um_jyblue1001_pll (Analog-PLL) tt_um_axi4lite2x2_top (AXI4-Lite 2M-2S Interconnect) tt_um_systolic_top (4x4 Systolic Matrix MAC Accelerator) tt_um_goose_game (Goose Game) tt_um_rongbin99_happyredmapleleaf_audio_chip (Audio Wave Generator Chip) tt_um_fp_id (FinSec-1: AS-68M Fingerprint Verification ASIC) tt_um_game_of_life (Demoscene: Game of Life) tt_um_ds_missile_command (Missile Command) tt_um_cmos_inverter (Reactive Plasma: CMOS Inverter) tt_um_nightplumeaki_tinypipcore (tinypipcore) tt_um_immrudul_w7khan (Mrudul and Wahhaj Demoscene F2025) tt_um_sohamgovande_transformer (Transformer) tt_um_isa084_uart_servo (UART Positioning PWM Interface) tt_um_wokwi_461265571826974721 (Bias Correction Filter) tt_um_8_bit_cpu (8-bit CPU) tt_um_richad (ADPPLS) tt_um_algofoogle_dottee (DOTTEE VGA demo) tt_um_sar_fms (SAR FSM) tt_um_kolontsov_journey (Journey) tt_um_fft_adityaamehra (64 Sample FFT ASIC) tt_um_lambda_clock (Lambda Clock) tt_um_ece298A_analog (ECE298A analog tile) tt_um_toivoh_demo (Orion Iron Ion [TTSKY26a demo competition]) tt_um_kilian_interference (Wave Lattice) tt_um_fabulous_sky_26a (Tiny FABulous FPGA) tt_um_Rats2012_WobblyBits (WobblyBits - A probabilistic computing chip) tt_um_rebelmike_asic_odyssey (2026: An ASIC Odyssey) tt_um_huyatieo_tinyqv_speck (Speck-V SoC) tt_um_mosbius (mini mosbius) tt_um_remedy_cpu (FFD16 cpu 16-bit) tt_um_vga_ocarina (Ocarina on VGA) tt_um_TinyGPU_v3 (Tiniest GPU V3) tt_um_santhosh_ring_osc (Ring Oscillator PVT Sensor & TRNG) tt_um_santhosh_xbar_ctrl (Memristive Crossbar Peripheral Controller) tt_um_santhosh_stdp_ctrl (Digital STDP Learning Controller) tt_um_santhosh_stoch_neuron (LFSR-Based Stochastic Neuron) tt_um_anweiteck_ldo (1V-LDO) tt_um_sriaxi4lite_top (Axi4_Lite) tt_um_bch_code_15_7_2 (Bose-Chaudhuri-Hocquenghem Code) tt_um_mastensg_ttsky26a_demo (Luz) tt_um_pakesson_vga_rocket (VGA Rocket) tt_um_adpll (ADPLL - All-Digital Phase-Locked Loop) tt_um_Bingyao_FCOTA (Self biased Single Ended Folded Cascoded OTA) tt_um_spacewar_top (Spacewar) tt_um_microlane_demo (microlane demo project) tt_um_NE567Mixer28 (ECG Front End) tt_um_wakita_mux8onehot_cap (Mux8onehot Pulldown Mosfet) tt_um_johshoff_metaballs (Metaballs v2) tt_um_tomvdsch_cyclonerunner (CycloneRunner) tt_um_lowprocess_wildcamping (PicoMIPS CPU) tt_um_canvas (Tiny Canvas) tt_um_snrlxd1068_MACs (Linear and Logarithmic MACs) tt_um_pakesson_simon64_128 (SIMON64/128) tt_um_AmitChen1415 (Tiny Blackjack) tt_um_ole_moller_double_dabble_SV (double_dabble_SV) tt_um_toivoh_demo_1tile (Single tile demo [TTSKY26a demo competition]) tt_um_shiho_space_invaders (Tiny Space Invaders) tt_um_analog_RO (Analog RO) tt_um_electron65_vga (VGA Clock Demo) tt_um_wokwi_457571266840151041 (3-Bit ALU) tt_um_katomata (Katomata - 1D Cellular Automata) tt_um_shimomi_analog (analog circuit) tt_um_toivoh_demo_4tile (Four tile demo [TTSKY26a demo competition]) tt_um_IEEE_open_silicon_FOSSEE (Ring oscillator VCO and Differential Amplifier) tt_um_lm_chip_top (Project Long Man: A Delay-Insensitive Interconnect) tt_um_AlephNaNsea_space_time_waves_and_filaments (Space-Time Waves and Filaments) tt_um_spacelizard_apu (Spacelizard APU) tt_um_wokwi_457569490272926721 (Letter S) tt_um_mau_top_4b (SIMD2 Math Accelerator Unit) tt_um_maze (Maze) tt_um_demoscenettsky (Algorithmic Pattern Generator) tt_um_wokwi_457572141968369665 (Arran's tinytapeout project) tt_um_maxluppe_ttsky26a_analog (Standard Digital Logic Cells Analog Comparator) tt_um_grammartile (GrammarTile) tt_um_bubble_sort (IEEE Bubble Sort Engine) tt_um_ahmed_nematallah_12_bit_adc (12-bit ADC) tt_um_bad_ode_plotter_vga (Bad VGA ODE Plotter) tt_um_wokwi_463706339714973697 (Demo 4-bit ALU 74181 variant) tt_um_wokwi_457569853853115393 (Jasper Tiny Tape Out Workshop) tt_um_wokwi_457560507752701953 (Osian Tiny Tapeout) tt_um_wokwi_457571501325987841 (Rola_Tiny Tapeout Template Workshop4Mar26) tt_um_wokwi_457571903121572865 (TT-wokwi-template) tt_um_wokwi_463380823859050497 (My_Name_on_7_Seg_display) tt_um_wokwi_457569584731832321 (Tiny Tapeout 9 Template Copy) tt_um_wokwi_457571826952995841 (Tiny Tapeout Novomorphic Design 1) tt_um_wokwi_457571349142937601 (Tiny Tapeout Secret First Letter Code) tt_um_wokwi_457571261877235713 (Tiny Tapeout Test) tt_um_wokwi_457582867322921985 (Tiny Tapeout Test GDS) tt_um_wokwi_457571135132600321 (Tiny Tapeout Test Gates) tt_um_wokwi_457571331577181185 (Tinytapeout_IA) tt_um_wokwi_457576779101727745 (tiny tapeout test gates) tt_um_wokwi_457571577702202369 (tj wowki) tt_um_wokwi_457572953060951041 (wokwi) tt_um_pettit_galton (Tiny Galton) tt_um_fountaincoder_top_abc (ABC Temporal Coincidence Detector) tt_um_prime_quine (Prime Quine) tt_um_ghtag_trinity_gf16 (Trinity GF16 Dot Product Accelerator) tt_um_LFSR (Configurable Galois LFSR) tt_um_Acrazt05_titan_proccesing_unit (Titan Proccesing Unit (TPU)) tt_um_essen (Digital) tt_um_alu_bns (6-bit Multi-Functional ALU) tt_um_gerardvt_spade_poc (Interactive XOR Plasma (Spade HDL)) tt_um_gerardvt_clash_poc (Interactive Triangle-Wave Plasma (Clash HDL)) tt_um_jackthoene_frogger (Frogger) tt_um_wokwi_463698873100105729 (IEEE Open Silicon 2026: UTB Logic Trivia Challenge: 8-bit Digital Lock) tt_um_wokwi_463666635153364993 (IEEE - Hex Counter and Logic Gate Validator) tt_um_ChristmasTree_MaligayangPasko (ChristmasTree_MaligayangPasko) tt_um_wokwi_463711763041599489 (IEEE Open Silicon 2026: UTB UART Transmitter basic) tt_um_tinytensorcore (TinyTensorCore) tt_um_uwasic_crypto (UWASIC Crypto) tt_um_topadi (time) tt_um_siliconimist (Siliconimist Demoscene) tt_um_neutern_0 (tt_um_neutern_0) tt_um_htfab_hsxo (HSXO) tt_um_madech_8bit_processor_vga (8-Bit Processor with VGA) tt_um_vga_clock (VGA clock) tt_um_usu_AXIS_MVMul (AXI-Stream Matrix Vector Multiplier) tt_um_weird_numbers (Weird Numbers) tt_um_bovi_cable_tester (Cable Tester) tt_um_libokuohai_asap_cpu_v2 (ASAP CPU v2) tt_um_LinusSkucas_pio (Tiny PIO) tt_um_thomas_ep_sensor (EP Sensor v7 (symmetric in-place thicken, Zhao-compliant)) tt_um_rakhanaufm_truerandom (Current-Starved Ring Oscillator Based True Random Number Generator) tt_um_parakeet (parakeet) tt_um_mcml_vco (MCML experiments) tt_um_tpu ( Tensor Processing Unit) tt_um_strasti (8-Bit ALU) tt_um_zed_analog (Analog design) tt_um_axi4lite_top (Axi4_Lite) tt_um_c4m_spsram_direct (TTSKY-SPSRAM-direct) tt_um_Onchip_Folded_Cascode_N_with_Bias (Folded Cascode N Type with Bias from Onchip Research Group) tt_um_htfab_hybrid (Telephone hybrid) tt_um_ilamparuthi_cfar (CFAR Radar Detector) tt_um_pakesson_glitcher (Glitcher) tt_um_advaittej_stopwatch (V-SPACE Demo: Command & Control Chronograph) tt_um_william_pll (Smartcard PLL Clock Generator) tt_um_Melody_Generator_JLANordhal (Melody Generator based on Markov Chains) tt_um_d_monteiro (Neuromorphic Processor (SNN)) tt_um_jacob_kebaso_4bit_cpu (Nibble - 4-bit CPU) tt_um_signal_detector (Signal_Detection_Processor) tt_um_catalinlazar_tinycore8 (TinyCore8) tt_um_chidam_secengine (Tiny Secure Telemetry Engine) tt_um_urish_usb_cdc (USB CDC (Serial) Device) tt_um_josenbm (9-Channel Frequency Counter with I2C + SPI DAC & ADC) tt_um_shalindra_vga_rings (Variable Speed and Colour Select VGA Rings) tt_um_dinukuk_MYVGA_GLIDER (DKTT01 - VGA Glider) tt_um_fibonacci_JoaoBortolace (Fibonacci Counter) tt_um_wokwi_461639934990157825 (4 bit unlock (IEEE)) tt_um_ctw_ldo (LDO Regulator Skywater 130nm)