964 AXI4-Lite 2M-2S Interconnect
964 : AXI4-Lite 2M-2S Interconnect
- Author: Kavinesh
- Description: Dual Master Dual Slave AXI4-Lite Interconnect
- GitHub repository
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- Clock: 50000000 Hz
AXI4-Lite Top Project
Overview
This project implements a self-contained AXI4-Lite system with a master and a slave connected inside a top-level wrapper (axi4lite_top).
It exposes a simple control interface so that reads and writes can be performed without directly driving AXI signals.
How It Works
- The top module (
axi4lite_top) instantiates:- An AXI4-Lite Master
- An AXI4-Lite Slave
- Instead of requiring the user to control all AXI signals, the top module provides a simplified interface:
ui_in[0]→ Start Writeui_in[2:1]→ Write Addressuio_in→ Write Dataui_in[4]→ Start Readui_in[3:2]→ Read Address
- When a transaction is started:
- The master drives the appropriate AXI4-Lite signals.
- The slave responds according to AXI protocol.
- When the transaction finishes,
uo_out[0]goes high (Done). - On reads, the data is returned via
uio_out.
Effectively, this module hides AXI4-Lite complexity and lets the user test simple memory-mapped transactions.
How to Test
Two types of testbenches are provided:
1. Verilog Testbench
- Located at
sim/axi4lite_tb.v. - Runs a reset → write → read → check sequence.
- Displays results in the simulator console.
2. Cocotb Testbench
- Located at
sim/test_axi4lite.py. - Uses Python for more flexible verification.
- Run with Icarus Verilog:
make SIM=icarus TOPLEVEL=axi4lite_top MODULE=test_axi4lite
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | m0_start_write | m0_rdata[0] | m1_start_write |
| 1 | m0_start_read | m0_rdata[1] | m1_start_read |
| 2 | m0_addr[0] | m0_rdata[2] | m1_addr[0] |
| 3 | m0_addr[1] | m0_rdata[3] | m1_addr[1] |
| 4 | m0_addr[2] | m0_rdata[4] | m1_addr[2] |
| 5 | m0_addr[3] | m0_rdata[5] | m1_addr[3] |
| 6 | m0_rdata[6] | m1_data[6] | |
| 7 | m0_rdata[7] | m1_data[7] |