271 Time Domain ADC
271 : Time Domain ADC
- Author: Nikitha D
- Description: Time Domain Comparator Based ADC
- GitHub repository
- Open in 3D viewer
- Clock: 1000000 Hz
Low-Power SAR-ADC for PPG Signal Acquisition
This repository includes the design files and simulation results of a 10-bit SAR ADC implemented in 180 nm CMOS technology, optimized for low-power biomedical applications such as photoplethysmogram (PPG) signal acquisition.
Project Overview
The primary objective of this project is to develop an efficient and accurate ADC tailored for low-power wearable devices. The design adopts a 10-bit monotonic SAR ADC architecture with a time-domain comparator to achieve power consumption in the microwatt range.
Architecture Details
The design employs a monotonic switching SAR ADC architecture, recognized for its high power efficiency and reduced capacitor array size.
The primary innovation is the time-domain comparator, implemented using a voltage-controlled delay line (VCDL), which significantly lowers power consumption compared to conventional dynamic comparators.
Key components:
-
Track-and-Hold (T/H) Switch: A bootstrapped switch used for accurate input signal sampling.
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Capacitive DAC (CDAC): Generates the reference levels for comparison.
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Time-Domain Comparator: A low-power comparator based on the VCDL approach.
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SAR Logic: Governs the successive approximation process.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | EN | CKO | DATA[1] |
| 1 | DATA[8] | DATA[0] | |
| 2 | DATA[7] | ||
| 3 | DATA[6] | ||
| 4 | DATA[5] | ||
| 5 | DATA[4] | ||
| 6 | DATA[3] | ||
| 7 | DATA[2] |
Analog pins
ua | PCB Pin | Internal index | Description |
|---|---|---|---|
| 0 | B0 | 6 | VCM |
| 1 | B1 | 7 | VIN |
| 2 | B3 | 9 | VIP |