811 Trinity GF16 Dot Product Accelerator
811 : Trinity GF16 Dot Product Accelerator
- Author: Dmitrii Vasilev · Trinity Stack
- Description: GF16 (Golden Float 16-bit, bias=31) dot product N=4. FPGA-validated at 323 MHz on XC7A100T. Apache 2.0. Anchor theorem: phi^2 + phi^-2 = 3 (Trinity identity, 84-theorem Coq base in t27). DOI: 10.5281/zenodo.19227877. Provenance: gHashTag/trinity-fpga#19, R-SI compliance map in gHashTag/trios assertions/igla_assertions.json. Step 1 of L-DPC3->L-DPC4->L-DPC5 silicon roadmap toward TRL 7 silicon-validation for PhD defense 2026-06-15.
- GitHub repository
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- Clock: 50000000 Hz
Trinity GF16 Dot Product
GF16 (Golden Float 16-bit) dot product N=4 accelerator with phi-structured bias=31 encoding.
How it works
The design computes a 4-element dot product in GF16 format:
- 4 parallel GF16 multipliers (combinational, with DSP-style booth encoding)
- 3 GF16 adders in tree reduction: p0+p1 → s01, p2+p3 → s23, s01+s23 → result
- GF16 format: 1 sign + 6 exponent (bias=31) + 9 mantissa
The default computes dot4([1,2,3,4], [1,2,3,4]) = 30.0 = 0x47C0.
How to test
After reset, the output should show:
uo_out= 0xC0 (result low byte)uio_out= 0x47 (result high byte)
Combined: 0x47C0 = GF16(30.0)
External hardware
No external hardware required. Directly observable on the output pins.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | load_mode | result_bit_0 | result_high_bit_0 |
| 1 | data_bit_0 | result_bit_1 | result_high_bit_1 |
| 2 | data_bit_1 | result_bit_2 | result_high_bit_2 |
| 3 | data_bit_2 | result_bit_3 | result_high_bit_3 |
| 4 | data_bit_3 | result_bit_4 | result_high_bit_4 |
| 5 | data_bit_4 | result_bit_5 | result_high_bit_5 |
| 6 | data_bit_5 | result_bit_6 | result_high_bit_6 |
| 7 | data_bit_6 | result_bit_7 | result_high_bit_7 |