297 SIMD2 Math Accelerator Unit

297 : SIMD2 Math Accelerator Unit

Design render

<img src="./img/blockdiagram_v3.png" alt="Initial Proposal Block Diagram" width="2259">

How it works

This 1x1 tile contains a math-accelerator unit (MAU) built around a 4-bit ALU pipeline.
A host device communicates with the MAU over a simple SPI-style interface using the TinyTapeout pins.

Each operation is encoded as a 20-bit “instruction word”:

  • 4 bits of opcode: which math operation to run (dot product, vector add/sub, sum of squares, distance², 2×2 determinant, scalar multiply, lerp, etc.)
  • Four 4-bit operands: a1, a2, b1, b2

The host sends this instruction 4 bits at a time on ui_in[3:0] while toggling:

  • uio_in[0] – SPI clock
  • uio_in[1] – write strobe (load data into the RX stage)

After 5 nibbles, the RX stage has a complete instruction and asserts a valid signal to the decode stage.
The decode stage:

  • Reads the opcode and selects which math operation to perform
  • Routes the four 4-bit operands into two internal “lanes” (X and Y)
  • Generates an alu_ctrl_t control signal package that is used to configure the ALU (pre-add, multiply mode, post-add/concat, add vs sub, etc.)
  • Sends a valid command to the ALU stage when the ALU indicates it is ready

alu_ctrl_t package

Field Width Description
pre_x_en 1 X lane pre-adder enable (0:passthrough, 1:add/sub)
pre_x_sub 1 X lane pre-adder mode (0:add, 1:sub)
mul_x_en 1 X lane mul enable (0:passthrough, 1:mul)
mul_x_sel 3 X lane mul input select (0:x0, 1:x1, 2:sqr 3:c 4:passthrough)
pre_y_en 1 Same as X but for Y lane
pre_y_sub 1 Same as X but for Y lane
mul_y_en 1 Same as X but for Y lane
mul_y_sel 3 Same as X but for Y lane
post_en 1 Post-adder en (0:concat, 1:add/sub)
post_sub 1 Post-adder mode (0:add, 1:sub)
post_sel 1 Post-adder input select (0:Y lane, 1:zero)

The ALU stage is a single-cycle 4-bit core with:

  • Per lane pre-adders (for adding or subtracting operand pairs)
  • Per lane multiplier blocks that can multiply, square, or pass values through
  • A combined post-stage that either concatenates the two lanes or adds/subtracts them

By enabling or bypassing these blocks, different opcodes implement functionality as outlined in the opcode table:

Operation OPCODE Formula Index a0 a1 b0 b1 Notes
NOOP 0x00 0. a<sub>0</sub>, a<sub>1</sub>, b<sub>0</sub>, b<sub>1</sub> x<sub>0</sub> x<sub>1</sub> y<sub>0</sub> y<sub>1</sub> returns input
DOT2 0x01 1. a<sub>0</sub>*a<sub>1</sub> + b<sub>0</sub>*b<sub>1</sub> x<sub>0</sub> y<sub>0</sub> x<sub>1</sub> y<sub>1</sub>
WSUM 0x02 1. x a y b
PROJ 0x03 1. x u<sub>x</sub> x u<sub>y</sub>
SUMSQ 0x04 1. x x y y
SCSUM 0x05 1. x c y c
VADD2 0x06 2. (a<sub>0</sub> + a<sub>1</sub>), (b<sub>0</sub> + b<sub>1</sub>) x0 y0 x1 y1
VSUB2 0x07 3. (a<sub>0</sub> - a<sub>1</sub>), (b<sub>0</sub> - b<sub>1</sub>) x0 y0 x1 y1 order into each lane matters
DIFF2 0x08 4. (a<sub>0</sub>*a<sub>1</sub>) - (b<sub>0</sub>*b<sub>1</sub>) x0 x1 y0 x1 order of lanes matter
DET2 0x09 4. x<sub>0</sub> y<sub>1</sub> y<sub>0</sub> x<sub>1</sub> order of lanes matter
DIFFSQ 0x0A 4. x x y y order of lanes matter
DIST2 0x0B 5. (a<sub>0</sub> - a<sub>1</sub>)² - (b<sub>0</sub> - b<sub>1</sub>)² x<sub>0</sub> x<sub>1</sub> y<sub>0</sub> y<sub>1</sub> order into and of each lane matters
POLY 0x0C 6. (a<sub>0</sub>*a<sub>1</sub>) + (b<sub>0</sub>) a x b -
SCMUL 0x0D 7. (a<sub>0</sub>*a<sub>1</sub>), (b<sub>0</sub>*b<sub>1</sub>) a b x y output concats to lower 9 bits for each lane
LERPX 0x0E 8. (a<sub>0</sub>) + (a<sub>1</sub>*(b<sub>1</sub> - b<sub>0</sub>)) x<sub>1</sub> c y<sub>0</sub> y<sub>1</sub> order into and of each lane matters, c = (y2-y1)/(x2-x1)
LERPY 0x0F 9. (b<sub>0</sub>) + (b<sub>1</sub>*(a<sub>1</sub> - a<sub>0</sub>)) x<sub>0</sub> x<sub>1</sub> y<sub>1</sub> c order into and of each lane matters, c = (y2-y1)/(x2-x1)
  • DOT2 – 2D dot product
  • VADD2 / VSUB2 – vector add/sub
  • SUMSQ, DIST2, DIFFSQ – sum of squares / distance² / squared difference
  • DET2 – 2×2 determinant
  • SCMUL, WSUM, PROJU, LERPX, LERPY – scalar multiply, weighted sums, projection, and simple linear interpolation

The ALU produces a 10-bit result plus a carry flag, which are stored in a small output register.

The TX stage then serializes this result back to the host:

  • Result bits are packed into 4-bit chunks and driven on uo_out[3:0]
  • The carry flag is exposed on uio_out[3]
  • The host clocks the data out using uio_in[0] (SPI clock) and uio_in[2] (read enable)

All stages use valid/ready handshakes, so if the host stops reading results, backpressure propagates and the ALU will stop accepting new commands without losing any results.

How to Test

This section provides a basic example of how to interact with the MAU hardware once it's fabricated on the TinyTapeout chip. The code snippet demonstrates loading a 40 bit (upper half of each byte is unused) instruction and reading the result through the psuedo SPI interface.

def send_instruction(tt, opcode, operands):
    #Load a 40 bit instruction into the MAU over 5 SPI clock cycles.
    #Args:
    #    tt: TinyTapeout interface object
    #    opcode: 8 bit operation code (e.g., 0x01 for DOT2)
    #    operands: List of four 8-bit operands [x0, x1, y0, y1]
    
    #Pack instruction into 5 bytes: [opcode, x0, x1, y0, y1]
    instruction_bytes = [opcode] + operands
    
    #Send each byte sequentially over the 8-bit input bus
    for byte in instruction_bytes:
        tt.input_byte = byte           #Place byte on ui_in[7:0]
        tt.uio.SPI_W = 1               #Assert write enable signal
        tt.clock_tick()                #Rising edge of SPI_clk to latch data
        tt.uio.SPI_W = 0               #Deassert write enable
    
def read_result(tt, num_bytes=3):
    #Read the result from the MAU over multiple SPI clock cycles.
    #Args:
    #    tt: TinyTapeout interface object
    #    num_bytes: Number of 8 bit chunks to read (3-5 depending on result size)
    #Returns:
    #    List of bytes representing the result (LSB first)

    result_bytes = []
    
    #Read each byte of the result sequentially
    for _ in range(num_bytes):
        tt.uio.SPI_R = 1                     #Assert read enable signal
        tt.clock_tick()                      #Rising edge of SPI_clk to output next byte
        result_bytes.append(tt.output_byte)  #Capture byte from ui_out[7:0]
        tt.uio.SPI_R = 0                     #Deassert read enable
    
    return result_bytes

#Example usage: Compute 2x1 vector dot product (DOT2)
#Operation: x0*x1 + y0*y1 = 2*3 + 4*5 = 6 + 20 = 26
send_instruction(tt, opcode=0x01, operands=[2, 3, 4, 5])

#Read 3 bytes of result (18-bit result + carry spans 3 bytes)
result = read_result(tt, num_bytes=3)

#Reconstruct the full result from received bytes
final_result = result[0] | (result[1] << 8) | (result[2] << 16)
print(f"DOT2 result: {final_result}")  # Expected: 26

The MAU processes instructions through its custom SPI interface, reading operands in sequence and returning results across multiple clock cycles to accommodate the 18-bit output width on an 8-bit bus.

IO

#InputOutputBidirectional
0in0o0u1
1in1o1u2
2in2o2u3
3in3o3u4
4in4o4u5
5in5o5u6
6in6o6u7
7in7o7u8

Chip location

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A probabilistic computing chip) tt_um_rebelmike_asic_odyssey (2026: An ASIC Odyssey) tt_um_huyatieo_tinyqv_speck (Speck-V SoC) tt_um_mosbius (mini mosbius) tt_um_remedy_cpu (FFD16 cpu 16-bit) tt_um_vga_ocarina (Ocarina on VGA) tt_um_TinyGPU_v3 (Tiniest GPU V3) tt_um_santhosh_ring_osc (Ring Oscillator PVT Sensor & TRNG) tt_um_santhosh_xbar_ctrl (Memristive Crossbar Peripheral Controller) tt_um_santhosh_stdp_ctrl (Digital STDP Learning Controller) tt_um_santhosh_stoch_neuron (LFSR-Based Stochastic Neuron) tt_um_anweiteck_ldo (1V-LDO) tt_um_sriaxi4lite_top (Axi4_Lite) tt_um_bch_code_15_7_2 (Bose-Chaudhuri-Hocquenghem Code) tt_um_mastensg_ttsky26a_demo (Luz) tt_um_pakesson_vga_rocket (VGA Rocket) tt_um_adpll (ADPLL - All-Digital Phase-Locked Loop) tt_um_Bingyao_FCOTA (Self biased Single Ended Folded Cascoded OTA) tt_um_spacewar_top (Spacewar) tt_um_microlane_demo (microlane demo project) tt_um_NE567Mixer28 (ECG Front End) tt_um_wakita_mux8onehot_cap (Mux8onehot Pulldown Mosfet) tt_um_johshoff_metaballs (Metaballs v2) tt_um_tomvdsch_cyclonerunner (CycloneRunner) tt_um_lowprocess_wildcamping (PicoMIPS CPU) tt_um_canvas (Tiny Canvas) tt_um_snrlxd1068_MACs (Linear and Logarithmic MACs) tt_um_pakesson_simon64_128 (SIMON64/128) tt_um_AmitChen1415 (Tiny Blackjack) tt_um_ole_moller_double_dabble_SV (double_dabble_SV) tt_um_toivoh_demo_1tile (Single tile demo [TTSKY26a demo competition]) tt_um_shiho_space_invaders (Tiny Space Invaders) tt_um_analog_RO (Analog RO) tt_um_electron65_vga (VGA Clock Demo) tt_um_wokwi_457571266840151041 (3-Bit ALU) tt_um_katomata (Katomata - 1D Cellular Automata) tt_um_shimomi_analog (analog circuit) tt_um_toivoh_demo_4tile (Four tile demo [TTSKY26a demo competition]) tt_um_IEEE_open_silicon_FOSSEE (Ring oscillator VCO and Differential Amplifier) tt_um_lm_chip_top (Project Long Man: A Delay-Insensitive Interconnect) tt_um_AlephNaNsea_space_time_waves_and_filaments (Space-Time Waves and Filaments) tt_um_spacelizard_apu (Spacelizard APU) tt_um_wokwi_457569490272926721 (Letter S) tt_um_mau_top_4b (SIMD2 Math Accelerator Unit) tt_um_maze (Maze) tt_um_demoscenettsky (Algorithmic Pattern Generator) tt_um_wokwi_457572141968369665 (Arran's tinytapeout project) tt_um_maxluppe_ttsky26a_analog (Standard Digital Logic Cells Analog Comparator) tt_um_grammartile (GrammarTile) tt_um_bubble_sort (IEEE Bubble Sort Engine) tt_um_ahmed_nematallah_12_bit_adc (12-bit ADC) tt_um_bad_ode_plotter_vga (Bad VGA ODE Plotter) tt_um_wokwi_463706339714973697 (Demo 4-bit ALU 74181 variant) tt_um_wokwi_457569853853115393 (Jasper Tiny Tape Out Workshop) tt_um_wokwi_457560507752701953 (Osian Tiny Tapeout) tt_um_wokwi_457571501325987841 (Rola_Tiny Tapeout Template Workshop4Mar26) tt_um_wokwi_457571903121572865 (TT-wokwi-template) tt_um_wokwi_463380823859050497 (My_Name_on_7_Seg_display) tt_um_wokwi_457569584731832321 (Tiny Tapeout 9 Template Copy) tt_um_wokwi_457571826952995841 (Tiny Tapeout Novomorphic Design 1) tt_um_wokwi_457571349142937601 (Tiny Tapeout Secret First Letter Code) tt_um_wokwi_457571261877235713 (Tiny Tapeout Test) tt_um_wokwi_457582867322921985 (Tiny Tapeout Test GDS) tt_um_wokwi_457571135132600321 (Tiny Tapeout Test Gates) tt_um_wokwi_457571331577181185 (Tinytapeout_IA) tt_um_wokwi_457576779101727745 (tiny tapeout test gates) tt_um_wokwi_457571577702202369 (tj wowki) tt_um_wokwi_457572953060951041 (wokwi) tt_um_pettit_galton (Tiny Galton) tt_um_fountaincoder_top_abc (ABC Temporal Coincidence Detector) tt_um_prime_quine (Prime Quine) tt_um_ghtag_trinity_gf16 (Trinity GF16 Dot Product Accelerator) tt_um_LFSR (Configurable Galois LFSR) tt_um_Acrazt05_titan_proccesing_unit (Titan Proccesing Unit (TPU)) tt_um_essen (Digital) tt_um_alu_bns (6-bit Multi-Functional ALU) tt_um_gerardvt_spade_poc (Interactive XOR Plasma (Spade HDL)) tt_um_gerardvt_clash_poc (Interactive Triangle-Wave Plasma (Clash HDL)) tt_um_jackthoene_frogger (Frogger) tt_um_wokwi_463698873100105729 (IEEE Open Silicon 2026: UTB Logic Trivia Challenge: 8-bit Digital Lock) tt_um_wokwi_463666635153364993 (IEEE - Hex Counter and Logic Gate Validator) tt_um_ChristmasTree_MaligayangPasko (ChristmasTree_MaligayangPasko) tt_um_wokwi_463711763041599489 (IEEE Open Silicon 2026: UTB UART Transmitter basic) tt_um_tinytensorcore (TinyTensorCore) tt_um_uwasic_crypto (UWASIC Crypto) tt_um_topadi (time) tt_um_siliconimist (Siliconimist Demoscene) tt_um_neutern_0 (tt_um_neutern_0) tt_um_htfab_hsxo (HSXO) tt_um_madech_8bit_processor_vga (8-Bit Processor with VGA) tt_um_vga_clock (VGA clock) tt_um_usu_AXIS_MVMul (AXI-Stream Matrix Vector Multiplier) tt_um_weird_numbers (Weird Numbers) tt_um_bovi_cable_tester (Cable Tester) tt_um_libokuohai_asap_cpu_v2 (ASAP CPU v2) tt_um_LinusSkucas_pio (Tiny PIO) tt_um_thomas_ep_sensor (EP Sensor v7 (symmetric in-place thicken, Zhao-compliant)) tt_um_rakhanaufm_truerandom (Current-Starved Ring Oscillator Based True Random Number Generator) tt_um_parakeet (parakeet) tt_um_mcml_vco (MCML experiments) tt_um_tpu ( Tensor Processing Unit) tt_um_strasti (8-Bit ALU) tt_um_zed_analog (Analog design) tt_um_axi4lite_top (Axi4_Lite) tt_um_c4m_spsram_direct (TTSKY-SPSRAM-direct) tt_um_Onchip_Folded_Cascode_N_with_Bias (Folded Cascode N Type with Bias from Onchip Research Group) tt_um_htfab_hybrid (Telephone hybrid) tt_um_ilamparuthi_cfar (CFAR Radar Detector) tt_um_pakesson_glitcher (Glitcher) tt_um_advaittej_stopwatch (V-SPACE Demo: Command & Control Chronograph) tt_um_william_pll (Smartcard PLL Clock Generator) tt_um_Melody_Generator_JLANordhal (Melody Generator based on Markov Chains) tt_um_d_monteiro (Neuromorphic Processor (SNN)) tt_um_jacob_kebaso_4bit_cpu (Nibble - 4-bit CPU) tt_um_signal_detector (Signal_Detection_Processor) tt_um_catalinlazar_tinycore8 (TinyCore8) tt_um_chidam_secengine (Tiny Secure Telemetry Engine) tt_um_urish_usb_cdc (USB CDC (Serial) Device) tt_um_josenbm (9-Channel Frequency Counter with I2C + SPI DAC & ADC) tt_um_shalindra_vga_rings (Variable Speed and Colour Select VGA Rings) tt_um_dinukuk_MYVGA_GLIDER (DKTT01 - VGA Glider) tt_um_fibonacci_JoaoBortolace (Fibonacci Counter) tt_um_wokwi_461639934990157825 (4 bit unlock (IEEE)) tt_um_ctw_ldo (LDO Regulator Skywater 130nm)