
The Lambda Clock is a highly-optimized full digital calendar and clock built for a 10-digit 7-segment multiplexed display architecture using three cascaded 74HC595 shift registers. It features a fully synchronous clock-enable domain (tick-based) that guarantees ASIC synthesis stability. It parses the base 1Hz and 1kHz ticks to manipulate independent BCD limits natively preventing binary-to-BCD resource explosion. It enforces leap-year restrictions automatically and incorporates an 8-state settings menu, tracking and individually updating Days, Months, Years, and Time. A built-in Alarm module is continuously checked against current active BCD time registers.
The clock provides an 8-stage interactive module.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | BTN_MODE | SCLK | |
| 1 | BTN_INC | RCLK | |
| 2 | BTN_DEC | DIO | |
| 3 | BTN_RST | BUZZER | |
| 4 | LED_SETUP | ||
| 5 | LED_ALARM | ||
| 6 | LED_ALARM_MATCH | ||
| 7 |