
This project implements a dual-mode Multiply-Accumulate (MAC) unit supporting both Linear and Logarithmic Number Systems. To accommodate the 8-bit I/O constraints of the Tiny Tapeout platform, the design utilizes a time-division multiplexed interface: two 8-bit operands are ingested over two consecutive clock cycles, while the internal 32-bit accumulation result is serialized and driven onto the 8-bit output pins over a span of four cycles.
The architecture supports two distinct operational modes:
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | in_data[0] | out_data[0] | i_mode[0] |
| 1 | in_data[1] | out_data[1] | i_mode[1] |
| 2 | in_data[2] | out_data[2] | i_valid |
| 3 | in_data[3] | out_data[3] | i_key |
| 4 | in_data[4] | out_data[4] | |
| 5 | in_data[5] | out_data[5] | |
| 6 | in_data[6] | out_data[6] | |
| 7 | in_data[7] | out_data[7] |