3 Inverted inverters
3 : Inverted inverters
- Author: Mikail Gedik
- Description: Long chain of inverters
- GitHub repository
- Open in 3D viewer
- Open in Tiny Tapeout Explorer
- Clock: 0 Hz
How it works
These are just a bunch of inverters in a long chain. This can maybe generate some randomness
How to test
To simulate combinatorial loops, we replace each not/nor with a dummy gate. Each dummy gate gets a seed and has an internal counter. That counter is used to give it schmitt-trigger like behaviour, so to simulate a real gate (even if it's a bad sim). The simulation takes forever and isn't very representative though.
Since the sim takes forever for the rng-stuff, we only test it locally and remotely we only check whether the registers work correctly
Gatelevel simulation cannot work, since we have combinatorial loops! It is therefore disabled
External hardware
Not really
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | A0 | D0o | D0i |
| 1 | A1 | D1o | D1i |
| 2 | A2 | D2o | D2i |
| 3 | A3 | D3o | D3i |
| 4 | A4 | D4o | D4i |
| 5 | A5 | D5o | D5i |
| 6 | SRC | D6o | D6i |
| 7 | WE | D7o | D7i |