
This project implements a hardware-efficient Constant False Alarm Rate (CFAR) signal detection engine, optimized for area-constrained silicon footprints. It processes a 14-bit digital input to dynamically adapt to varying noise floors and detect valid target signals.
Input Mapping: To bypass the standard 8-pin input limit, the design concatenates standard inputs with bidirectional pins configured as inputs:
ui_in[7:0]: Lower 8 bits of the incoming signal.uio_in[5:0]: Upper 6 bits of the incoming signal (uio_oe = 0).{uio_in[5:0], ui_in[7:0]}).CFAR Architecture: Instead of a memory-heavy sliding window, this design utilizes an Infinite Impulse Response (IIR) running average to estimate the background noise threshold.
threshold = (threshold + signal) >> 1.uo_out[7]).Initialization:
clk.rst_n = 0) to clear the internal threshold registers.rst_n = 1) to begin normal operation.Baseline / Noise Floor Test (No Detection):
ui_in = 50, uio_in = 0).0 and the detection flag (uo_out[7]) remains 0.Target Detection Test (Spike):
ui_in = 250, uio_in = 0).threshold * GAIN condition. The 7-segment display immediately updates to 1 and the detection flag (uo_out[7]) goes HIGH (1).(Note: To maximize pin availability for the 14-bit data bus, no additional external peripherals, such as buzzers, are used).
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ADC bit 0 | 7-seg a | ADC bit 8 |
| 1 | ADC bit 1 | 7-seg b | ADC bit 9 |
| 2 | ADC bit 2 | 7-seg c | ADC bit 10 |
| 3 | ADC bit 3 | 7-seg d | ADC bit 11 |
| 4 | ADC bit 4 | 7-seg e | ADC bit 12 |
| 5 | ADC bit 5 | 7-seg f | ADC bit 13 |
| 6 | ADC bit 6 | 7-seg g | unused |
| 7 | ADC bit 7 | Detection output | unused |