683 8-bit CBILBO
683 : 8-bit CBILBO
- Author: Devesh Bhaskaran, Om Shivshankar Shigarkanti, Garima Bajpayi
- Description: Concurrent Built--In Logic BlockIn Logic Block Observer for Memory Test
- GitHub repository
- Clock: 40000000 Hz
How it works
In this Verilog code, we implement a BILBO (Built-In Logic Block Observer) shift register with multiple stages, using a combination of logic gates (AND, XOR), D flip-flops (DFF), and multiplexers (MUX) for feedback and shifting operations. We include input and output paths for Tiny Tapeout and support asynchronous reset and clocked logic. The modules interact to store and shift data, providing internal feedback and driving outputs for observation.
How to test
To test this project, we would create a testbench that provides stimulus for the inputs (ui_in, uio_in, clk, rst_n) and checks the outputs (uo_out, uio_out, uio_oe). We would simulate the shifting and feedback behavior of the BILBO shift register, verifying that the data is properly shifted and the feedback logic functions correctly across all stages of the register.
External hardware
No external hardware required for this project.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui_in[0] | uo_out[0] | uio[0] |
| 1 | ui_in[1] | uo_out[1] | uio[1] |
| 2 | ui_in[2] | uo_out[2] | uio[2] |
| 3 | ui_in[3] | uo_out[3] | uio[3] |
| 4 | ui_in[4] | uo_out[4] | uio[4] |
| 5 | ui_in[5] | uo_out[5] | uio[5] |
| 6 | ui_in[6] | uo_out[6] | uio[6] |
| 7 | ui_in[7] | uo_out[7] | uio[7] |