198 4x4 Multiplier
198 : 4x4 Multiplier
- Author: Fajr Baig, Sahana Long
- Description: 4-by-4 Bit Multiplier, Lab 3
- GitHub repository
- Clock: 0 Hz
How it works
This is a 4 by 4 bit multiplier designed in Verilog using structural designs.
How to test
To run test, refer to test/README.md. To add new test, modify test/test.py.
External hardware
None.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | q[0] | p[0] | |
| 1 | q[1] | p[1] | |
| 2 | q[2] | p[2] | |
| 3 | q[3] | p[3] | |
| 4 | m[0] | p[4] | |
| 5 | m[1] | p[5] | |
| 6 | m[2] | p[6] | |
| 7 | m[3] | p[7] |