746 Verilog test project
746 : Verilog test project
- Author: Alexander Symons
- Description: It adds the input and the IO pins
- GitHub repository
- Clock: 0 Hz
How it works
It adds the dedicated input to an internal register every clock cycle Least significant bits: dedicated output Most significant bits: bidirectional output
How to test
Put numbers on the input and see the accumulated value on all the leds
External hardware
Switches on inputs, leds on outputs and bidirectionals
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui_in[0] | uo_out[0] | uio_out[0] |
| 1 | ui_in[1] | uo_out[1] | uio_out[1] |
| 2 | ui_in[2] | uo_out[2] | uio_out[2] |
| 3 | ui_in[3] | uo_out[3] | uio_out[3] |
| 4 | ui_in[4] | uo_out[4] | uio_out[4] |
| 5 | ui_in[5] | uo_out[5] | uio_out[5] |
| 6 | ui_in[6] | uo_out[6] | uio_out[6] |
| 7 | ui_in[7] | uo_out[7] | uio_out[7] |