299 carry_select
299 : carry_select
- Author: Juan, Leyang
- Description: This project designs a 8-bit carry select adder.
- GitHub repository
- Clock: 0 Hz
How it works
The 8-bit carry select adder works through the full adder and mux. The Carry Select Adder works by essentially using two ripple adders, with one having cin = 0 and the other cin = 1. Through this procedure, we are able to speed up the calculation of selecting which sum depending on our cin.
The ripple adder works by using a cascade of several full adders connected in series with each other. Each full adder is resposible for their adding their corresponding bits from both inputs and outputs their carryout to the carryin of the next full adder until both inputs have been fully added together. The ripple adder, and by extension the carry select adder is simple to implement and requires minimal logic gates to implement, making it inexpensive and space-efficient compared to other methods of addition. However, there is a delay due to the carry propagation which limits the ripple adder (and therefore the carry-select adder) in its effective speed with larger bitwidth inputs. However, for this application (8-bits), this adder is very efficient in both space and speed.
This project uses 'https://github.com/FCHXWH823/Verilog-Adders' as reference.
How to test
We tested all the combinations. This means two 8 bits input sum to a 8 bit output, and we ignore the carry out bit.
Therefore, we expect both the input and the output to be in the range of 0 to 255.
External hardware
We did not use any external hardware.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | a[0] | sum[0] | b[0] |
| 1 | a[1] | sum[1] | b[1] |
| 2 | a[2] | sum[2] | b[2] |
| 3 | a[3] | sum[3] | b[3] |
| 4 | a[4] | sum[4] | b[4] |
| 5 | a[5] | sum[5] | b[5] |
| 6 | a[6] | sum[6] | b[6] |
| 7 | a[7] | sum[7] | b[7] |