333 an lfsr with synaptic neurons (excitatory or inhibitatory)
333 : an lfsr with synaptic neurons (excitatory or inhibitatory)
- Author: kai juarez-jimenez
- Description: each bit edge in the LFSR will mimic synaptic input that either excites / inhibits the next “neuron” , shwoing behaviors similar to how synapses manage signal in nns.
- GitHub repository
- Clock: 0 Hz
How it works
this project implements a neuromorphic-inspired Linear Feedback Shift Register (LFSR) with "synaptic neurons" that simulate excitatory/inhibitory responses. each bit in the LFSR behaves like a neuron, where transitions (rising/falling edges) from 0 to 1 or 1 to 0 generate excitatory or inhibitory signals, simulating synaptic inputs in neural networks. these signals modify the LFSR’s feedback path, resulting in pseudo-random output sequences that mimic synaptic interactions by either enhancing (excitatory) or suppressing (inhibitory) activity.
additionally, this design allows for customizable seed inputs, set through external input pins, enabling users to initialize the LFSR with a specific seed to observe varying sequence outputs. this feature provides added flexibility and control over the pseudo-random behavior.
How to test
- clock initialization: Run a clock signal to provide timing for the LFSR operation.
- reset: hold the reset pin active (low) to initialize the LFSR state with the selected seed.
- seed testing: configure the seed by setting the ui_in input pins, then observe the LFSR output sequence through uo_out.
- cycle observation: monitor the output sequence over multiple clock cycles to verify pseudo-random behavior, and repeat for different seed values for varied sequences.
External hardware
N/A
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | LFSR Seed Bit 0 | LFSR Output Bit 0 | |
| 1 | LFSR Seed Bit 1 | LFSR Output Bit 1 | |
| 2 | LFSR Seed Bit 2 | LFSR Output Bit 2 | |
| 3 | LFSR Seed Bit 3 | LFSR Output Bit 3 | |
| 4 | LFSR Seed Bit 4 | LFSR Output Bit 4 | |
| 5 | LFSR Seed Bit 5 | LFSR Output Bit 5 | |
| 6 | LFSR Seed Bit 6 | LFSR Output Bit 6 | |
| 7 | LFSR Seed Bit 7 | LFSR Output Bit 7 |