Four micro tiles were combined into a single Tiny Tapeout tile to analyze power coupling within the Power Distribution Network.
Use uio[1:0] to see the output of the micro-tile projects.
The project generates a delayed clock signal utilizing eight distinct delay lines
Nothing to test here.
A Time-to-Digital Converter (TDC) is embedded in one tile and interfaced with the sensor. It measures the time interval between the clock signal from the sensor and the delayed clock signal generated by the sensor.
Nothing to test here, an experimental basis.
It includes an activation signal capable of enabling 16 ring oscillators simultaneously, primarily to induce power stress for monitoring the Power Distribution Network (PDN)."
Same as the previous design of ROs, just placed in another tile to add power stress
# | Input | Output | Bidirectional |
---|---|---|---|
0 | in[0] | out[0] | sel[0] |
1 | in[1] | out[1] | sel[1] |
2 | in[2] | out[2] | |
3 | in[3] | out[3] | |
4 | in[4] | out[4] | |
5 | in[5] | out[5] | |
6 | in[6] | out[6] | |
7 | in[7] | out[7] |