238 8-bit-CARRY_SKIP
238 : 8-bit-CARRY_SKIP
- Author: Aaquil Kasham, Temiloluwa Omomuwasan
- Description: 8 bit input adder
- GitHub repository
- Clock: 0 Hz
How it works
This project implements an 8-bit carry-skip adder using a combination of ripple-carry and skip logic for enhanced performance. The adder is divided into two 4-bit sections. The lower 4 bits compute the initial partial sum and generate a carry-out, which is then either passed directly to the upper 4-bit section or skipped, depending on the carry-propagate signal. This design reduces the delay associated with carry propagation, making it more efficient than a conventional ripple-carry adder. The final 8-bit sum is registered and outputted in sync with the clock signal.
How to test
To test the carry-skip adder:
Load the design into your simulation environment.
Set the ui_in and uio_in inputs with the desired 8-bit values for addition.
The result of the addition will appear on uo_out after each rising edge.
Verify that the output matches expected values by comparing uo_out with the sum of the inputs.
For more extensive testing, a testbench can be used to automate input combinations and check results across various cases.
External hardware
No external hardware is required for this project. List external hardware used in your project (e.g. PMOD, LED display, etc), if any
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | a[0] | sum[0] | b[0] |
| 1 | a[1] | sum[1] | b[1] |
| 2 | a[2] | sum[2] | b[2] |
| 3 | a[3] | sum[3] | b[3] |
| 4 | a[4] | sum[4] | b[4] |
| 5 | a[5] | sum[5] | b[5] |
| 6 | a[6] | sum[6] | b[6] |
| 7 | a[7] | sum[7] | b[7] |