680 mips.sv
680 : mips.sv
- Author: Eric Smith
- Description: The MIPs core example from Weste & Harris
- GitHub repository
- Clock: 1000000 Hz
How it works
This is the example processor core from Weste & Harris written by Max Yi ([email protected]) and [email protected] 12/9/03 https://pages.hmc.edu/harris/cmosvlsi/4e/code/mips.tar.gz
How to test
Carefully
External hardware
Need a program store.
More to come later.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | memdata[0] | writedata[0] | adr[0] |
| 1 | memdata[1] | writedata[1] | adr[1] |
| 2 | memdata[2] | writedata[2] | adr[2] |
| 3 | memdata[3] | writedata[3] | adr[3] |
| 4 | memdata[4] | writedata[4] | adr[4] |
| 5 | memdata[5] | writedata[5] | adr[5] |
| 6 | memdata[6] | writedata[6] | memread |
| 7 | memdata[7] | writedata[7] | memwrite |