678 Basic model for Systollic array implementation of LIF
678 : Basic model for Systollic array implementation of LIF
- Author: Sulaiman Islam
- Description: A model for systolic array implementation of LIF neurons. Hazard cases have been taken into account such as overstimulation of LIF nuerons with bypass cases.
- GitHub repository
- Clock: 0 Hz
How it works
The model represents how a generative implementation of SNN training can be implemented in verilog. Hazards that were predicted were that of LIF overstimulation due to excessive accumilation of the multiply accumilate MAC operations. In order to prevent this I implemented bypass conditions that made regulated the LIF inputs to choose between 0 and the output of the MAC operatios. The LIF would only take in the value of the MAC operation when the threeshold for firing was reached by the output of the MAC. One clock cylce later the MAC Accumilation would be reset. This was a weight stationary implemenation that had fixed constant weights on each of the MACS. Several Blocks of these weight stationary MACS could be implemented with their respective LIFS in theory, however due to size restrictions there is only one small block in the Top module. The user input ui_in is used to drive the MAC inputs. The uo_out individual bits were used to drive the spike to inidcate that the bypass had occured and that the LIF had spiked.
How to test
Using ui_in to vary X and checking uo_out for expected behavior based on the MAC operations.
External hardware
N/A
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | input current bit [0] | State variable bit [0] | |
| 1 | input current bit [1] | State variable bit [1] | |
| 2 | input current bit [2] | State variable bit [2] | |
| 3 | input current bit [3] | State variable bit [3] | |
| 4 | input current bit [4] | State variable bit [4] | |
| 5 | input current bit [5] | State variable bit [5] | |
| 6 | input current bit [6] | State variable bit [6] | |
| 7 | input current bit [7] | State variable bit [7] | spike bit |