676 Verilog ring oscillator V2
676 : Verilog ring oscillator V2
- Author: algofoogle (Anton Maurovic)
- Description: Multiple simple ring oscillators by instantiating sky130 inv_2 inverter rings
- GitHub repository
- Clock: 0 Hz
What is this?
Everyone has done a ring oscillator using inverter cells. Now it's my turn!
I already submitted tt09-ring-osc on TT09 and rather than muck that up with extra stuff I decided to submit this alternate version which features:
- 4 simple independent rings instead of 1, hoping to run at different speeds:
ring_125: 125 inverters, maybe 112MHz out? Could be too fast for IO.ring_251: 251 inverters, hopefully good for ~56MHz.ring_501: 501 inverters, ~28MHz.ring_1001: 1001 inverters, ~14MHz.
- Some other PWM experiments on faster ring oscillators.
Approximate frequences are estimated on the assumption that each inverter introduces a delay of ~70ps.
These use verilog to instantiate the rings of (an odd number of) sky130_fd_sc_hd__inv_2 cells.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | pwm2_in[0] | ring_125 | dummy |
| 1 | pwm2_in[1] | ring_251 | pwm3a_out |
| 2 | pwm3_in[0] | ring_501 | |
| 3 | pwm3_in[1] | ring_1001 | |
| 4 | c0_3 | ||
| 5 | pwm3a_in[0] | c1_3 | |
| 6 | pwm3a_in[1] | c2_5 | pwm2_out |
| 7 | pwm3a_in[2] | c3_5 | pwm3_out |