256 Array Multiplier :: Quicker, easier and cheaper to make your own chip!

How it works

An array multiplier is a combinational circuit that performs binary multiplication by generating and summing partial products. Here’s how a 4x4 array multiplier operates:

Binary Multiplicand and Multiplier: A 4x4 multiplier takes two 4-bit binary numbers (e.g., ( A = A_3 A_2 A_1 A_0 ) and ( B = B_3 B_2 B_1 B_0 )) as inputs. Each bit in ( A ) is multiplied by each bit in ( B ), creating 16 partial products.
Partial Product Generation: Each bit in ( A ) is ANDed with each bit in ( B ), forming a matrix of partial products. For instance, if ( A = 1011 ) and ( B = 1101 ), then ( A_3 \times B_3 ), ( A_3 \times B_2 ), and so forth are calculated.
Shifting and Summing: Each row of partial products corresponds to a shifted version based on the position of the bits in ( B ). For example, the row generated by ( A_3 ) will be shifted three places to the left.
Adding Partial Products: The shifted partial products are summed column by column, similar to traditional addition in binary, often using full adders or half adders.
Final Product: The result is an 8-bit product that represents the multiplication of the two 4-bit inputs.

Here's a visual representation of how an array multiplier works:

graph TD A[Multiplicand A - Bits A3 A2 A1 A0] B[Multiplier B - Bits B3 B2 B1 B0] subgraph Partial_Products A3B0[A3 * B0] --> A3B1[A3 * B1] --> A3B2[A3 * B2] --> A3B3[A3 * B3] A2B0[A2 * B0] --> A2B1[A2 * B1] --> A2B2[A2 * B2] --> A2B3[A2 * B3] A1B0[A1 * B0] --> A1B1[A1 * B1] --> A1B2[A1 * B2] --> A1B3[A1 * B3] A0B0[A0 * B0] --> A0B1[A0 * B1] --> A0B2[A0 * B2] --> A0B3[A0 * B3] end Sum[Sum of Partial Products] Output[Final Product] A --> Partial_Products B --> Partial_Products Partial_Products --> Sum Sum --> Output

How to test

To test the array multiplier:

Set up the multiplier by providing binary inputs for both the multiplicand (A) and the multiplier (B).
Run the simulation or test in hardware to verify that each partial product is calculated correctly.
Ensure that the partial products are properly shifted and summed to produce the final product.
Compare the final output with the expected result from standard binary multiplication to confirm accuracy.

External hardware

No external hardware is required for this project. The array multiplier can be tested within a simulation environment or with an FPGA setup if hardware verification is needed.

#	Input	Output
0	q[0]	p[0]
1	q[1]	p[1]
2	q[2]	p[2]
3	q[3]	p[3]
4	m[0]	p[4]
5	m[1]	p[5]
6	m[2]	p[6]
7	m[3]	p[7]

256 Array Multiplier