A Pseudo-Differential Time to Digital Converter (TDC)
The TDC has one analog input that is then split into start and stop signals. Because this TDC has a resolution of around 80 ps, it would be difficult to provide signals with such a small phase difference, that is why there is an extra variable delay circuit that delays the stop signal relative to the start signal. You can change the stop signal delay by configuring the digital input. To test the circuit drive the stop signal for a given configuration of delay.
No external hardware needed.
# | Input | Output | Bidirectional |
---|---|---|---|
0 | stop fine delay 0 | tdc bit 0 | stop coarse delay 4 |
1 | stop fine delay 1 | tdc bit 1 | start fine delay 0 |
2 | stop fine delay 2 | tdc bit 2 | start fine delay 1 |
3 | stop fine delay 3 | tdc bit 3 | start fine delay 2 |
4 | stop coarse delay 0 | tdc bit 4 | start fine delay 3 |
5 | stop coarse delay 1 | tdc bit 5 | start enable |
6 | stop coarse delay 2 | tdc bit 6 | |
7 | stop coarse delay 3 | tdc bit 7 |
ua | PCB Pin | Internal index | Description |
---|---|---|---|
0 | B5 | 11 | stop |