263 Time to Digital Converter

263 : Time to Digital Converter

Design render
  • Author: Jeremiasz Hauck
  • Description: Phase difference measuring circuit with digital output
  • GitHub repository
  • Clock: 0 Hz

How it works

The circuit includes a time-to-digital converter (TDC) and a variable delay line. The circuit's output is the TDC's result, which consists of eight stages, producing eight outputs. This chip serves no practical purpose beyond testing the TDC circuit.

The TDC operates by utilizing flip-flops as time comparators and a delay line that generates delayed versions of the input start signal. It measures the phase difference between the start and stop signals by propagating the start signal through the delay line while using the stop signal as the clock for the flip-flops. The outputs of the flip-flops are high if the delayed start signal arrives before the stop signal and low if the delayed start signal arrives after the stop signal. By counting the number of high outputs, the phase difference between the start and stop signals can be determined with a resolution equal to one delay unit. Below is a diagram of a TDC with two stages.

TDC circuit

The implemented TDC achieves a resolution of approximately 75 ps in post-layout simulations. Because it is challenging to provide external signals with phase differences as small as 75 ps, the circuit is designed to use a single input signal as both the start and stop signals. To test various outputs, the stop signal is delayed relative to the start signal. The architecture of the chip, featuring the TDC and the stop signal variable delay line, is shown below.

Circuit architecture

The chip layout is shown below, with boxed sections corresponding to the components in the architecture diagram.

Layout

To generate the TDC transfer curve, the start and stop signals were provided with varying phase differences. The simulation results for the TDC term_4 output are shown below. The term_4 output goes high when the phase difference between the signals is 377 ps.

TDC term_4 output simulation

Once the phase difference that triggers each TDC output is determined, a transfer curve can be plotted, as shown below.

TDC transfer curve

The stop signal delay is implemented using a variable delay line comprising fine and coarse delay stages. The fine delay stage offers a step size of 25 ps, while the coarse delay stage provides a step size of 145 ps in post-layout simulations. Below are the simulation outputs for the coarse and fine delay stages. The delay line is configured using digital inputs. The start signal also has an associated delay line, but only with fine delay stages. This additional delay allows fine-grained control when the coarse delay steps are too large, enabling smaller phase differences between signals.

Coarse delay

Fine delay

How to test

The chip has one analog input, 14 digital inputs, and 8 digital outputs. To clear the TDC from a previous measurement, drive the start enable input low, and after a short delay, drive the stop input high. To test the TDC, vary the digital input values while applying a square wave to the analog stop signal.

The fine delay is controlled using thermometer encoding, while the coarse delay is controlled using one-hot encoding. An input of all zeros is valid for both encoding schemes.

External hardware

Additional hardware, such as a Raspberry Pi (RPi) and a level shifter, is required to drive the analog and digital inputs.

IO

#InputOutputBidirectional
0stop fine delay 0tdc bit 0stop coarse delay 4
1stop fine delay 1tdc bit 1start fine delay 0
2stop fine delay 2tdc bit 2start fine delay 1
3stop fine delay 3tdc bit 3start fine delay 2
4stop coarse delay 0tdc bit 4start fine delay 3
5stop coarse delay 1tdc bit 5start enable
6stop coarse delay 2tdc bit 6
7stop coarse delay 3tdc bit 7

Analog pins

uaPCB PinInternal indexDescription
0B511stop

Chip location

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implementation of LIF) tt_um_algofoogle_tt09_ring_osc2 (Verilog ring oscillator V2) tt_um_dff_mem (dff_mem) tt_um_nomuwill (16 Bit Izhikevich Neuron) tt_um_digital_clock_example (7-Segment Digital Desk Clock) tt_um_udxs (Basic Perceptron + ReLU) tt_um_matrix_mult (Basic Matrix-Vector Multiplication) tt_um_db_MAC (8 bit MAC Unit) tt_um_anas_7193 (Programmable PWM Generator) tt_um_flyingfish800 (Verilog test project) tt_um_project (Basic LIF Neuron) tt_um_lifn (Integrate-and-Fire Neuron Circuit) tt_um_wokwi_413921836641882113 (ovl abc chip) tt_um_mickey_pll (pll) tt_um_rejunity_e2m0_x_i8_matmul (E2M0 x INT8 Systolic Array) tt_um_michaelmcculloch_alu (Michaels Tiny Tapeout ALU) tt_um_dog_BILBO (8-bit CBILBO) tt_um_stochastic_integrator_tt9_CL123abc (Stochastic Integrator) tt_um_vga_clock (VGA clock) tt_um_z2a_rgb_mixer (RGB Mixer demo) tt_um_samkho_two_channel_square_wave_generator (TwoChannelSquareWaveGenerator) tt_um_mattvenn_r2r_dac_3v3 (Analog 8 bit 3.3v R2R DAC) tt_um_b_10_array_multiplier (Lab B Group 10 Array Multiplier) tt_um_urish_giant_ringosc (Giant Ring Oscillator (3853 inverters)) tt_um_htfab_caterpillar (Simon's Caterpillar) tt_um_anders_tt_6502 (tt6502) tt_um_wokwi_414123795172381697 (TinySnake) tt_um_oscillating_bones (Oscillating Bones) tt_um_r2r_dac (4-bit R2R DAC) tt_um_tinytinfoil_saradc_dac (Noise test for a CDAC capacitor chain) tt_um_purdue_socet_uart (SoCET UART) tt_um_rejunity_sn76489 (Classic 8-bit era Programmable Sound Generator SN76489) tt_um_rejunity_ay8913 (Classic 8-bit era Programmable Sound Generator AY-3-8913) tt_um_tommythorn_cgates (Cgates) tt_um_09eksdee (eksdee) tt_um_13hihi31_tdc (Time to Digital Converter) tt_um_rejunity_decoder (ternary, E1M0, E2M0 decoders) tt_um_analog_example (Digital OTA) tt_um_kailinsley (Dynamic Threshold Leaky Integrate-and-Fire) tt_um_C6_array_multiplier (tt09-C6-array-multiplier) tt_um_rejunity_vga_test01 (VGA Drop (audio/visual demo)) tt_um_wallento_4bit_toycpu (4-Bit Toy CPU) tt_um_warp (Warp) tt_um_algofoogle_tt09_ring_osc3 (Verilog ring oscillator V3) tt_um_kev_ma_matmult222 (2-bit 2x2 Matrix Multiplier) tt_um_wokwi_414041465275103233 (SK Test Workshop) tt_um_rejunity_vga_logo (VGA Tiny Logo (1 tile)) tt_um_toivoh_demo (Sequential Shadows [TT08 demo competition]) tt_um_liaf (A simple leaky integrate and fire neuron) tt_um_wokwi_413879612498222081 (Clocked Display) tt_um_wokwi_413919625901452289 (Encoder) tt_um_wokwi_413919442353385473 (Encoder) tt_um_wokwi_413919540668975105 (First Tapeout Chip - OCR) tt_um_wokwi_413918022277139457 (Half Adder) tt_um_wokwi_414120435095328769 (Kai's Death Adder) tt_um_wokwi_413919775044656129 (Kevin Project) tt_um_lif_network_MR (Leaky Neuron Network) tt_um_lsnn_hschweig (Neuromorphic Hardware for SNN LSTM) tt_um_wokwi_413387065963362305 (Project) tt_um_Nishanth_RISCV (RISCV Processor Design) tt_um_wokwi_413883347321632769 (Test_project) tt_um_KoushikCSN_RISCV (RISCV Processor Design) tt_um_wokwi_414120868401584129 (Tian TT9) tt_um_wokwi_414120391864616961 (Tiniest of tapeouts) tt_um_wokwi_414120458938907649 (Who knows what's happening Tiny Tapeout) tt_um_wokwi_413919833599252481 (YoshiTP) tt_um_wokwi_414118269335820289 (chip_fab) tt_um_wokwi_414121281003682817 (dummy) tt_um_wokwi_414124471705253889 (sarah's first chip) tt_um_ccu_goatgate (tiny cipher 4 bit key) tt_um_wokwi_414120526876163073 (2 input multiplexor) tt_um_lif_ZB (Tutorial: Simple LIF Neuron) Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available