618 triggerer
618 : triggerer
- Author: Krzysztof Skrzynecki
- Description: Module capturing timestamps of input signals (triggers) referenced to internal counter
- GitHub repository
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- Clock: 50000000 Hz
How it works
This module is capturing high edges in input lines (triggers) and stores the timestamp when this happened. Period of internal counter is order of 30ms (24b).
Main clk is used for intetrnal logic and timestamp timer. When edge on trigger input is detected, time is captured (max capture frequency is clk/2, but preferably even lower).
When data to read is available it is signalled on data reayd output pin.
In order to read the data, first set high enable pin, hold it and while holding start clocking data clk input. (max data clk rate should be over 2 times slower than clk). Read the data on output pin on data clk rising edge. 3 bytes should be read. Most significant bit is transferred first.
How to test
Just hope that this works (tested maually on simulator exactly once..)
External hardware
None, but signal generator bursting a few edges into trig input might be helpful
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | DAT_CLK | DAT_RDY | |
| 1 | DAT_ENA | DAT_OUT | |
| 2 | TRIGG_0 | ||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |