718 Bitty

718 : Bitty

Design render

Bitty System: RTL Design and Verification Framework

This project implements a custom 16-bit processing system, including hardware modules for program counter (PC), instruction fetch, branch logic, UART communication, and integration with the BittyEmulator for co-simulation. The provided system allows robust testing of a Verilog-based design using a Python-based cocotb testbench. The testbench orchestrates data transfer via UART, interacts with shared memory, and verifies execution against the emulator.

System Overview

Core Components

Без имени

  1. Program Counter (PC):

    • Handles sequential and branch-based instruction execution.
    • Interfaces directly with the branch logic for control flow changes.
  2. Instruction Fetch Unit:

    • Reads and decodes instructions from memory.
    • Supplies data to the rest of the system.
  3. Branch Logic:

    • Evaluates branch conditions and modifies the PC as needed.
  4. UART Module:

    • Supports data exchange between the testbench and the DUT.
    • Operates with customizable baud rates and clock frequencies.
  5. Bitty Emulator:

    • Acts as a functional reference model.
    • Validates the outputs and internal states of the hardware implementation.
    • Includes: Control Unit, registers, ALU, mux

Bitty Top Module

Memory Map
  • Shared Memory:
    • Synchronizes data between the testbench, the hardware design (DUT), and the emulator.
    • Supports up to 256 entries.
  • Instruction Set:
    • Defined in instructions_for_em.txt, loaded by the testbench for execution. Here’s the revised version written as a description of a fully implemented system:

Instruction Set Architecture: Fully Implemented 16-bit Processor

Overview

This document outlines the complete instruction set architecture (ISA) for a 16-bit processor, detailing its capabilities, operations, and encoding formats. The ISA is designed to deliver robust functionality for arithmetic, logical, control flow, and memory operations while maintaining a simple, efficient structure.

The processor's instruction set enables dynamic memory interactions, conditional branching, and a wide range of data manipulation tasks, providing the foundation for executing complex algorithms and software applications.


Instruction Set

Arithmetic and Logical Operations

The processor supports both register-to-register and immediate operations, enabling developers to perform computations efficiently.

Register-to-Register Instructions:

изображение

  1. add rx, ry: Adds the value in ry to rx.

    • Operation: rx = rx + ry
  2. sub rx, ry: Subtracts the value in ry from rx.

    • Operation: rx = rx - ry
  3. and rx, ry: Performs a bitwise AND between rx and ry.

    • Operation: rx = rx & ry
  4. or rx, ry: Performs a bitwise OR between rx and ry.

    • Operation: rx = rx | ry
  5. xor rx, ry: Performs a bitwise XOR between rx and ry.

    • Operation: rx = rx ^ ry
  6. shl rx, ry: Shifts the bits in rx left by the number of positions specified in ry.

    • Operation: rx = rx << ry
  7. shr rx, ry: Shifts the bits in rx right by the number of positions specified in ry.

    • Operation: rx = rx >> ry
  8. cmp rx, ry: Compares the values in rx and ry.

    • Operation:
      • rx = 0 if rx == ry
      • rx = 1 if rx > ry
      • rx = 2 if rx < ry
Immediate Instructions:

изображение

  1. addi rx, #i: Adds the immediate value #i to rx.

    • Operation: rx = rx + #i
  2. subi rx, #i: Subtracts the immediate value #i from rx.

    • Operation: rx = rx - #i
  3. andi rx, #i: Performs a bitwise AND between rx and #i.

    • Operation: rx = rx & #i
  4. ori rx, #i: Performs a bitwise OR between rx and #i.

    • Operation: rx = rx | #i
  5. xori rx, #i: Performs a bitwise XOR between rx and #i.

    • Operation: rx = rx ^ #i
  6. shli rx, #i: Shifts rx left by #i positions.

    • Operation: rx = rx << #i
  7. shri rx, #i: Shifts rx right by #i positions.

    • Operation: rx = rx >> #i
  8. cmpi rx, #i: Compares the value in rx with the immediate value #i.

    • Operation:
      • rx = 0 if rx == #i
      • rx = 1 if rx > #i
      • rx = 2 if rx < #i

Memory Operations

Load and Store Instructions:

изображение

  1. ld rx, (ry): Loads the value from the memory address stored in ry into register rx.

    • Operation: rx = mem[ry]
  2. st rx, (ry): Stores the value in register rx into the memory address stored in ry.

    • Operation: mem[ry] = rx
Encoding Format:
  • Bits 15-13 (Rx): Destination register for ld or source register for st.
  • Bits 12-10 (Ry): Register holding the memory address.
  • Bits 9-3 (Reserved): Reserved for future extensions, currently set to zero.
  • Bit 2 (L/S): Load/Store flag (0 for ld, 1 for st).
  • Bits 1-0: Instruction format identifier (11 for memory operations).

Conditional Branching

The processor supports conditional branching with a dedicated encoding format for efficient control flow.

Conditional Branch Instructions:

изображение

  1. bie addr: Branch if equal (condition flag EQ is set).
  2. big addr: Branch if greater (condition flag GT is set).
  3. bil addr: Branch if less (condition flag LT is set).
Encoding Format:
  • Bits 15-4 (Immediate): Encodes the branch target address.
  • Bits 3-2 (Condition):
    • 00: Equal
    • 01: Greater than
    • 10: Less than
  • Bits 1-0 (Format): Instruction format identifier (10 for conditional branching).

Here’s a detailed step-by-step guide for users to set up and test their system with the assembler and testbench:


How to Use the System

Before running the testbench, you must first prepare the assembly instructions or machine code. Here’s how:

Step 1: Prepare Instructions
  1. Option 1: Generate machine code automatically
    Run the CIG_run.py script to generate output.txt automatically with pre-defined assembly instructions.

    python3 CIG_run.py
    

    This will create output.txt containing machine code.

  2. Option 2: Write custom assembly instructions
    If you prefer to write your own instructions, directly create or modify the output.txt file. These instructions will later be disassembled for further testing.

Step 2: Disassemble Machine Code

Disassemble the output.txt file (machine code) to generate instructions_for_em.txt (assembly code):

./er_tool -d -i output.txt -o instructions_for_em.txt

This step ensures that the instructions in instructions_for_em.txt are ready for use in the testbench.


Running the Testbench

Once you have the instructions_for_em.txt file ready, navigate to the bitty-tt10/test directory and execute the testbench using make:

cd ~/bitty-tt10/test
make

The testbench will:

  1. Load the instructions from instructions_for_em.txt.
  2. Simulate UART communication for instruction execution.
  3. Compare the outputs of the DUT (Device Under Test) with expected results.
  4. Log the results, including any discrepancies, into uart_emulator_log.txt.

Testbench Overview
Assembling Code

To convert instructions_for_em.txt into machine code (if needed for testing):

./er_tool -a -i instructions_for_em.txt -o output.txt 
Disassembling Code

To convert machine code (output.txt) back into assembly:

./er_tool -d -i output.txt -o instructions_for_em.txt 

Practical Workflow Example
  1. Generate Machine Code:
    Run CIG_run.py to create machine code:

    python3 CIG_run.py
    
  2. Disassemble Code:
    Use the er_tool to create instructions_for_em.txt:

    ./er_tool -d -i output.txt -o instructions_for_em.txt
    
  3. Run Testbench:
    Navigate to the test directory and run the testbench:

    cd ~/bitty-tt10/test
    make
    

Key Features of the Testbench
  • Simulated UART Communication: Generates UART signals and captures DUT transmissions.
  • Instruction Execution: Fetches and executes instructions in real-time.
  • State Validation: Logs and compares DUT outputs with expected results.
  • Error Reporting: Logs any mismatches in uart_emulator_log.txt.

Following these steps ensures smooth operation from writing or generating instructions to verifying the system’s functionality. If you encounter issues, double-check the prepared files or logs for guidance. Let me know if you need further clarification!

How to Use

Setup
  1. Prerequisites:

    • Install Python and cocotb.
    • Ensure Verilog simulation tools (Verilator, Iverilog) are installed.
    • Use the following command to install the dependencies:
       pip install -r requirements.txt
    
  2. Input Files:

    • Place the instruction file (instructions_for_em.txt) in the working directory.
    • Modify the file as needed to test specific scenarios.
  3. Shared Libraries:

    • Ensure BittyEmulator.py and shared_memory.py are in the project directory.
Running the Test
  1. Execute the cocotb testbench:

    make
    
  2. Observe the test results in the terminal and logs:

    • Successes and failures are detailed in uart_emulator_log.txt.

External Hardware

This system does not require external hardware. UART communication is emulated within the testbench.


Files Overview

Verilog Files
  • <module_name>.v: Contains the RTL design files for the system.
  • tb_<module_name>.v: Top-level Verilog testbench wrapper.
Python Files
  • test_bitty.py: The cocotb testbench described above.
  • BittyEmulator.py: Emulator for reference model validation.
  • shared_memory.py: Utility for creating shared memory structures.

Limitations and Future Work

  1. Hardware Expansion:

    • Current implementation is limited to basic arithmetic and control operations.
    • Future iterations could incorporate advanced features like pipelining or caching.
  2. Error Handling:

    • Expand error reporting for unresolved signals during simulation.
  3. Scalability:

    • Extend memory and instruction sets for larger programs.

This project demonstrates a robust framework for RTL verification, combining software co-simulation with hardware modeling for high-fidelity testing and validation.

IO

#InputOutputBidirectional
0rx_data_bittx_data_bit
1sel_baude_rate[0]
2sel_baude_rate[1]
3
4
5
6
7

Chip location

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tt_um_favoritohjs_scroller (VGA Scroller) tt_um_tt08_wirecube (Wirecube) tt_um_vga_glyph_mode (Glyph Mode) tt_um_a1k0n_vgadonut (VGA donut) tt_um_roy1707018 (RO) tt_um_sign_addsub (CMOS design of 4-bit Signed Adder Subtractor) tt_um_patater_demokit (Patater Demo Kit Waggling Rainbow on a Chip) tt_um_simon_cipher (simon_cipher) tt_um_thexeno_rgbw_controller (RGBW Color Processor) tt_um_demosiine_sda (DemoSiine) tt_um_bytex64_munch (Munch) tt_um_cfib_demo (cfib Demoscene Entry) tt_um_Richard28277 (4-bit ALU) tt_um_betz_morse_keyer (Morse Code Keyer) tt_um_nvious_graphics (nVious Graphics) tt_um_ezchips_calc (8-Bit Calculator) tt_um_hack_cpu (HACK CPU) tt_um_ring_divider (Divided Ring Oscillator) tt_um_ephrenm_tsal (TSAL_TT) tt_um_kapilan_alarm (Alarm Clock) tt_um_stochastic_addmultiply_CL123abc (Stochastic Multiplier, Adder and Self-Multiplier) tt_um_dlfloatmac (DL float MAC) tt_um_faramire_rotary_ring_wrapper (Rotary Encoder WS2812B Control) tt_um_i2c_peripheral_stevej (i2c peripherals: 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Sound Generator AY-3-8913) tt_um_tommythorn_cgates (Cgates) tt_um_09eksdee (eksdee) tt_um_rejunity_decoder (ternary, E1M0, E2M0 decoders) tt_um_kailinsley (Dynamic Threshold Leaky Integrate-and-Fire) tt_um_rejunity_vga_test01 (VGA Drop (audio/visual demo)) tt_um_wallento_4bit_toycpu (4-Bit Toy CPU) tt_um_warp (Warp) tt_um_algofoogle_tt09_ring_osc3 (Verilog ring oscillator V3) tt_um_kev_ma_matmult222 (2-bit 2x2 Matrix Multiplier) tt_um_rejunity_vga_logo (VGA Tiny Logo (1 tile)) tt_um_liaf (A simple leaky integrate and fire neuron) tt_um_lif_network_MR (Leaky Neuron Network) tt_um_lsnn_hschweig (Neuromorphic Hardware for SNN LSTM) tt_um_Nishanth_RISCV (RISCV Processor Design) tt_um_KoushikCSN_RISCV (RISCV Processor Design) tt_um_ccu_goatgate (tiny cipher 4 bit key) tt_um_lif_ZB (Tutorial: Simple LIF Neuron) tt_um_z2a_rgb_mixer (RGB Mixer demo) tt_um_vga_clock (VGA clock) tt_um_synth_simple_mm (synth_simple) tt_um_gus16 (GUS16 CPU) tt_um_rejunity_ternary_dot (Ternary 128-element Dot Product) tt_um_virantha_enigma (Enigma - 52-bit Key Length) tt_um_atomNPU (AtomNPU) tt_um_alphaonesoc (AlphaOneSoC) tt_um_gxrii_spi_sevenseg (SPI 7-segment display) tt_um_urish_simon (Simon Says memory game) tt_um_branch_pred (TinyTapeout Minimal Branch Predictor) tt_um_xor_encryption (Xor-Logic) tt_um_MAC_Accelerator_OnSachinSharma (MAC Operation) tt_um_moody_mimosa (Moody-mimosa) tt_um_wrapper (6Digit7SegClock) tt_um_MichaelBell_tinyQV (TinyQV Risc-V SoC) tt_um_devmonk_ay8913 (Classic 8-bit era Programmable Sound Generator AY-3-8913) tt_um_toivoh_demo_tt10 (Orion Iron Ion [TT08 demo competition]) tt_um_2048_vga_game (2048 sliding tile puzzle game (VGA)) tt_um_gamepad_pmod_demo (Gamepad Pmod Demo) tt_um_tinytapeout_logo_screensaver (VGA Screensaver with Tiny Tapeout Logo) tt_um_mattvenn_spi_test (SPI test) tt_um_huffman_coder (Huffmann_Coder) tt_um_multiplier_tt10 (Vedic multiplier) tt_um_schoeberl_wildcat (Wildcat RISC-V) tt_um_kentrane_tinyspectrum (Tiny piano) tt_um_i2c_regf (Asynchronous I2C Registerfile Interface) tt_um_tappu_tobias1012 (Tappu) tt_um_mp_lif_schor (mp_LIF_neuron) tt_um_asgerwenneb (Custom SRAM) tt_um_Strider93 (digital LIF Neuron) tt_um_wokwi_422960078645704705 (Hero on Tape) tt_um_keszocze_ssmcl (SSMCl) tt_um_luke_clock (TT10_Luke_Clock) tt_um_enjens (Verilog based clock to 7-segment counter) tt_um_UartMain (XOR Cipher) tt_um_torurstrom_async_lock (Asynchronous Locking Unit) tt_um_larva (LaRVa CPU) tt_um_zhouzhouthezhou_adder (tt10_zhouzhouthezhou_adder) tt_um_jp_cd101_saw (KCH CD101 Saw Synth) tt_um_hpdl1414_uart_atudoroi (TT10 HPDL 1414 Uart) tt_um_jun1okamura_test0 (7-segment with LFSR) tt_um_strau0106_simple_viii (simple-viii) tt_um_obriensp_jtag (JTAG TAP) tt_um_10_vga_crossyroad (Crossyroad) tt_um_bilal_trng (TRNG) tt_um_space_invaders_game (Space Invaders ASIC) tt_um_sushi_demo (zc-sushi-demo) tt_um_kch_cd101 (kch cd101) tt_um_uart_bgdtanasa (ttUART) tt_um_zedulo_spitest1 (SimpleSPIdev) tt_um_daobaanh_rng (RNG_test) tt_um_gcd_stephan (15bit GCD) tt_um_spacewar (XY Spacewar) tt_um_gregac_tiny_nn (Tiny Neural Network Accelerator) tt_um_log_afpm (16-bit Logarithmic Approximate Floating Point Multiplier) tt_um_rkarl_Spiral (TT_spiralPattern) tt_um_led_jellyant (ledtest) tt_um_project_tt10 (Simple shift Reg) tt_um_DaDDS (DaDDS) tt_um_nithishreddykvs (Pulse Width Modulation) tt_um_monishvr_fifo (Synchronous FIFO) tt_um_reemashivva_fifo (Asynchronous FIFO) tt_um_save_buffer_hash_table (Tiny Hash Table) tt_um_drum_goekce (DRUM) tt_um_rte_sine_synth (Sine Synth) tt_um_tiny_shader_mole99 (Tiny Shader) tt_um_flummer_ltc (Linear Timecode (LTC) generator) tt_um_bitty (Bitty) tt_um_ole_moller_priority_encoder_to_7_segment_decoder (Priority-encoder) tt_um_algofoogle_vga (IHP VGA demo) tt_um_ultra_tiny_cpu (UltraTiny-CPU) tt_um_uwasic_dinogame (UW ASIC - Optimized Dino) tt_um_Qwendu_spi_fpu (SPI FPU) tt_um_aditya_patra (Priority-Encoded Arbiter) tt_um_4_bit_ALU (ALU) tt_um_htfab_checkers (Overengineered Checkers) tt_um_brukstus_tdc_with_spi (TDC with SPI) tt_um_toniklippeo (toni_clk_gen) tt_um_spi_pwm_djuara (spi_pwm) tt_um_iitbbs (CYCLIPSONIC) tt_um_wokwi_411783629732984833 (BINCounterAndGates) tt_um_wokwi_412635532198550529 (tt09-pettit-wokproc-trainer) tt_um_wokwi_413385294512575489 (Duffy) tt_um_wokwi_413387014781302785 (L display) tt_um_wokwi_413387093939376129 (sphereinabox hello) tt_um_wokwi_413387190167208961 (Will It NAND?) tt_um_wokwi_group_1 tt_um_wokwi_group_2 tt_um_wokwi_group_3 tt_um_wokwi_group_4 tt_um_wokwi_group_5 tt_um_wokwi_group_6 tt_um_wokwi_group_7 tt_um_wokwi_group_8 tt_um_wokwi_group_9 tt_um_wokwi_group_10 tt_um_wokwi_group_11 tt_um_wokwi_group_12 tt_um_tetrap_triggerer (triggerer) tt_um_wokwi_group_13 tt_um_multiplier_group_1 tt_um_multiplier_group_2 tt_um_multiplier_group_3