196 7 Segment Decode

196 : 7 Segment Decode

Design render
  • Author: Jack Clayton
  • Description: ASIC implementation of a university CPLD project which drives 4 multiplexed 7 segment displays, and scans a multiplexed keypad.
  • GitHub repository
  • Open in 3D viewer
  • Clock: 5000 Hz

How it works

The serial protocol implemented in this design consists of a simple single byte packet which instructs the CPLD which column of the keypad to multiplex into MISO, which screen should be displaying data, and what number should be displayed on the screen. The screen select signal also doubles up as instructing which row of the keypad to be scanned. Data is sent Most Significant Bit (MSB) first.

SPI Protocol visual bit representations

SPI Protocol bit definitions

SPI example byte 0xD7

Verilog block diagram

The high impedance programming state is not implemented in this ASIC. It is represented as a bit out instead.

Keep in mind: This system is clocked by the SPI clock, and therefore requires constant clocking to function.

How to test

Build the supporting hardware as described in the schematic found in "Exteral hardware". Create a system which transmits SPI bytes, according to specifications in "How it works". The system will display your desired digits on the selected screens.
You may also use the MISO to implement a 4x4 keypad, which is interpreted by the system creating the SPI bytes. This will not be detailed as to how to implement.

External hardware

Main external system schematic:

Main schematic

Simple keypad:

Keypad schematic

IO

#InputOutputBidirectional
0Out7S[0]ScreenSel[0]
1MOSIOut7S[1]ScreenSel[1]
2ENOut7S[2]ScreenSel[2]
3RESETOut7S[3]ScreenSel[3]
4KeyPlxr[0]Out7S[4]High-Z
5KeyPlxr[1]Out7S[5]
6KeyPlxr[2]Out7S[6]
7KeyPlxr[3]MISO

Chip location

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