Adds 2 4bit numbers together Verilog then goes into an always block where it maps the sum to a number on the 8 segment If the sum is a number the 8 segment cannot display, it will show a . Overflow is not handled
Use the dip switches to set the input, will add the upper 4 bits to the lower 4 bits
N/A
# | Input | Output | Bidirectional |
---|---|---|---|
0 | ui_0 | uo_1 | |
1 | ui_1 | uo_2 | |
2 | ui_2 | uo_3 | |
3 | ui_3 | uo_4 | |
4 | ui_4 | uo_5 | |
5 | ui_5 | uo_6 | |
6 | ui_6 | uo_7 | |
7 | ui_7 | uo_8 |