12 Cgates
12 : Cgates
- Author: Tommy Thorn
- Description: Testing two different Cgate implementations and rings
- GitHub repository
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- Clock: 0 Hz
How it works
(This is a variant of tt06-ncl-lfsr, but with different C-gate implementations)
Muller's C-gate is a state-holding element with two inputs A and B, and an output Q. Q holds the previous state unless A == B in which case it takes on this value. There are many ways to implement the C-gate. In this design, we try two: building it from a latch and building it out of combinatorial logic. The two inputs ui[0] and ui[1] are fed to two C-gates Cl and Cc, build with a latch and combinatorial logic respectively. Their respective outputs are wired to uo[0] and uo[1].
We also build four rings from this, with uo[2] and uo[3] being the output of a four stage build from Cl and Cc gates respectively. Similar for uo[4]/uo[5] except using 16 stage rings and uo[6]/uo[7] for (TBD) stage rings.
How to test
Set ui[0] and ui[1] different values and verify that uo[0]/uo[1] only changes when both agree. Observe uo[7:2] and look for transitions.
External hardware
For the basic test the rp2040 on the bringup board should be enough for the ring test, an oscilloscope is [probably] required.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | A | Ql | |
| 1 | B | Qc | |
| 2 | R4l | ||
| 3 | R4c | ||
| 4 | R16l | ||
| 5 | R16c | ||
| 6 | RTBDl | ||
| 7 | RTBDc |