This design uses a set of registers to divide the clock and combinational logic to convert binary values into decimal for display.
Fixed Period Mode:
Pseudo-Random Period Mode:
After reset, the counter will increment by one every second, assuming a 10MHz input clock.
You can experiment by modifying Inputs[1:0] to:
Only TT-EVB.
This is the first test project designed by “jun1okamura”, supported by OpenSUSI (non-profit) and AIST Solutions inc. in Japan.
# | Input | Output | Bidirectional |
---|---|---|---|
0 | sel0 | segment a | counter bit 0 |
1 | sel1 | segment b | counter bit 1 |
2 | compare bit 13 | segment c | counter bit 2 |
3 | compare bit 14 | segment d | counter bit 3 |
4 | compare bit 15 | segment e | counter bit 4 |
5 | compare bit 16 | segment f | counter bit 5 |
6 | compare bit 17 | segment g | counter bit 6 |
7 | compare bit 18 | dot | counter bit 7 |