A simple "inner project" drives a seven-segment display from either an internal 4-bit counter or from a 4-bit value presented on ui[4:1]
.
The "outer project" adds a boundary scan register and JTAG TAP that supports the following instructions:
IDCODE
SAMPLE
/PRELOAD
EXTEST
INTEST
CLAMP
BYPASS
At startup, the project will drive the seven-segment display from either the internal 4-bit counter (if ui[0]
is low) or from ui[4:1]
(if ui[0]
is high).
A BSDL file is provided for testing the TAP and boundary scan register. A tool like UrJTAG can be used to control the output pins (via the EXTEST
instruction) or to test the inner project (via the INTEST
instruction).
JTAG adapter connected to uio[7:4]
# | Input | Output | Bidirectional |
---|---|---|---|
0 | output_mode | seven_segment | |
1 | output_value[0] | seven_segment | |
2 | output_value[1] | seven_segment | |
3 | output_value[2] | seven_segment | |
4 | output_value[3] | seven_segment | TCK |
5 | seven_segment | TMS | |
6 | seven_segment | TDI | |
7 | seven_segment | TDO |