19 instrumented_ring_oscillator :: Quicker, easier and cheaper to make your own chip!

How it works

Preface: This is probably not a component you want if you want a reliable end device. This is intended to allow studying the decay (or persistence) of high-frequency "modes" which are generally very undesirable.

This project uses ring oscillators with muxes on the inputs to allow setting an initial state or "seed". This can be configured using a clock (in3) and data (in2) similar to SPI (positive edge clocks the data in. The in0 line is the enable to start the oscillator running, and in1 is a HOLD line that blocks one stage so that the normal long period can be obtained. in7:in4 select the number of stages (2*n + 5). In order to have selectable stages without a really big mux (which would have a very different propagation speed than the other stages), two muxes per stage are used, some of them bypassing some of the chain to get the desired number of muxes. This diagram shows the short mux paths as pipes ("|").

Note that when less than 25 stages are used, all inverters are still driven, but some outputs are not used. Note that the seed state is a FIFO fed in at the little end - it's always updatable (though it's state should not impact operation).

How to test

Hook up an analyzer / scope to the output & bidirectional channels.16 phases are driven out.
Select the number of stages (in7:in4).
If desired, seed the initial state using in3, in2. It's a
Drive enable (in0) high and watch the chaos to see if it stabilizes to the longest frequency, or if high frequency modes persist.
The hold (in1) can be briefly drivent to get to the longest frequency.

External hardware

A logic analyzer will probably be the most useful tool for this - For FPGA testing, I used a Digilent Digital Discovery (DD) with this projects outputs going to DD channels 0-15, and using DD channels 24-31 to drive the project inputs. A multi-channel oscilloscope might also be interesting to use with this.

#	Input	Output	Bidirectional
0	enable	phase[0]	phase[8]
1	hold	phase[1]	phase[9]
2	bdat	phase[2]	phase[10]
3	bclk	phase[3]	phase[11]
4	n_stages[0]	phase[4]	phase[12]
5	n_stages[1]	phase[5]	phase[13]
6	n_stages[2]	phase[6]	phase[14]
7	n_stages[3]	phase[7]	phase[15]

19 instrumented_ring_oscillator