98 UltraTiny-CPU
98 : UltraTiny-CPU
- Author: Roméo Estezet
- Description: Simple 8-Bit CPU
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
The UltraTiny-CPU is a minimal 8-bit CPU with a small instruction set (ALU, data flow, and control flow). It has:
- Accumulator (ACC) as the primary register
- Register B as a secondary register
- Program Counter (PC) to fetch instructions from an internal 16-byte memory
- Instruction Register (IR) to decode the current operation
The CPU features a “load mode” that writes data or instructions into the memory and a “run mode” that fetches and executes those instructions:
-
Load Mode:
- Activated when
ui[7] == 1. - The address to write is placed on
ui[3:0]. - The data/instruction byte is supplied on
uio[7:0]and written into memory.
- Activated when
-
Run Mode:
- Activated when
ui[7] == 0andena == 1. - The CPU fetches the instruction from memory at
PC, decodes it, performs the operation (arithmetic, logic, load/store, or branch), and increments or modifiesPCaccordingly. - The result of arithmetic/logical operations is stored in the accumulator (
ACC), and its value is driven ontouo[7:0].
- Activated when
How to test
-
Enter Load Mode (
ui[7] = 1):- Provide a memory address (0 to 15) on
ui[3:0]. - Provide an 8-bit instruction/data on
uio[7:0]. - Toggle
clkto store that byte into internal memory. - Repeat for as many instructions/data bytes as needed.
- Provide a memory address (0 to 15) on
-
Run the Program:
- Switch to Run Mode (
ui[7] = 0). - Ensure
ena = 1(the CPU is enabled). - The CPU will begin fetching instructions starting at address 0.
- Observe the accumulator outputs on
uo[7:0]to see results of execution.
- Switch to Run Mode (
If your design environment simulates clocking and signals, you can watch the memory load process and the CPU fetch/execute cycle in a waveform viewer or on actual hardware.
External hardware
No external hardware is strictly required. The UltraTiny-CPU operates solely with its on-chip 16-byte memory and the provided I/O pins. You can optionally attach an external logic analyzer or an LED display to the accumulator outputs (uo[7:0]) if you want a visual indication of the CPU state. Otherwise, all interfacing can be done directly via the pin signals.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Memory load address bit 0 (when ui[7]=1) | Accumulator output bit 0 | Data bus bit 0 for load mode (input), otherwise tri-stated |
| 1 | Memory load address bit 1 (when ui[7]=1) | Accumulator output bit 1 | Data bus bit 1 for load mode (input), otherwise tri-stated |
| 2 | Memory load address bit 2 (when ui[7]=1) | Accumulator output bit 2 | Data bus bit 2 for load mode (input), otherwise tri-stated |
| 3 | Memory load address bit 3 (when ui[7]=1) | Accumulator output bit 3 | Data bus bit 3 for load mode (input), otherwise tri-stated |
| 4 | Unused (available for other custom inputs) | Accumulator output bit 4 | Data bus bit 4 for load mode (input), otherwise tri-stated |
| 5 | Unused (available for other custom inputs) | Accumulator output bit 5 | Data bus bit 5 for load mode (input), otherwise tri-stated |
| 6 | Unused (available for other custom inputs) | Accumulator output bit 6 | Data bus bit 6 for load mode (input), otherwise tri-stated |
| 7 | Load mode enable (1=program load, 0=run) | Accumulator output bit 7 | Data bus bit 7 for load mode (input), otherwise tri-stated |