233 Rounding error
233 : Rounding error
- Author: Edwin Török
- Description: Competition entry
- GitHub repository
- Open in 3D viewer
- Clock: 25250000 Hz
How it works
This started out as an attempt to implement a ray tracer in 2 TT tiles. However there isn't enough room for a proper one, precision has to be limited, which leads to rounding errors that are unavoidable.
So embrace rounding errors, and make them the primary feature!
The RTL was written using HardCaml, that emits Verilog. For convenience the generated verilog is committed into the source tree, so no additional tools are needed
The "eye" Z coordinate is animated between 3.5 and 4.5 in 256 steps, where each frame is one step.
The design runs at 640x480@60Hz.
How to test
Set pin ui[0] to 0 to run the default demo.
Set pin ui[0] to 1 to show a test image with color bars.
Provide a 25.25 MHz clock on the clk pin (RP2040 should be able to provide this with no jitter).
Or if you can try 25.175 MHz instead, but this will have some jitter. YMMV.
The audio is a very simple mix of hsync and vsync signals.
External hardware
Connect according to the Demoscene rules
-
VGA output using Leo's VGA PMOD on pins
uo[0-7], connected to a monitor supporting 640x480 resolution. -
Audio output using Mike's audio PMOD on
uio[7]
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | test mode (0=no, 1=yes) | r1 | |
| 1 | g1 | ||
| 2 | b1 | ||
| 3 | vsync | ||
| 4 | r0 | ||
| 5 | g0 | ||
| 6 | b0 | ||
| 7 | hsync | PWM output |