164 Delay Line
164 : Delay Line
- Author: Ashley J. Robinson
- Description: A simple delay line with instrumentation
- GitHub repository
- Clock: 50000000 Hz
How it works
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A delay line output changes based on time delay of different variables such as process, voltage and temperature.
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There are may different delay line architectures.
- https://springerplus.springeropen.com/articles/10.1186/s40064-016-2090-z.
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This implementation is a simple tapped delay line.
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The continually changing data races through a chain of inverters.
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The chain is sampled at different stages to become a digital signal.
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An edge detection circuit is used find the rising which is then converted in a binary value.
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A bank of flops is used to sample 8 sequential rising edge values.
How to test
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https://github.com/ashleyjr/tt04-delay-line/blob/main/src/test/silicon_test.py
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This python script uses pyserial to run a set of tests on the design
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python3 silicon_test.py --help
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UART
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The UART is the only interface to the design
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9600 baud
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Least significant bit first
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1 Start bit
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8 Data bits
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No parity bit
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1 Stop bit
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Taken from https://github.com/ashleyjr/rtl-uart
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The bottom 4 bits [3:0] of the UART frame make up the command
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4'h0: Shift In
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Shift the top 4 bits [7:4] of the frame in to memory
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The memory is shifted 4 places to the left
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The data is placed in to the bottom 4 bits [3:0]
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This command is to test the silicon and debug software
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4'h1: Shift Out
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Shift the top 8 bits [39:32] of memory out to UART Tx
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The memory is shifted 8 places to the left
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4'h2: Full Sample
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Take a full 32-bit sample from the delay line and place in memory
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The sample is placed in to the bottom 32 bits [31:0]
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The shift out command may be used to read the sample
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4'h3: Scope
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Take 8 samples from the delay line at a 25MHz sample rate
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These sample use the edge detection logic to find the position of the rising edge
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These samples are 5 bits wide
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The samples are shifted in to the memory
- Sample 0: [39:35]
- Sample 1: [34:30]
- Sample 2: [29:25]
- Sample 3: [24:20]
- Sample 4: [19:15]
- Sample 5: [14:10]
- Sample 6: [9:5]
- Sample 7: [4:0]
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The shift out command may be used to read the sample
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4'h4 to 4'hF inclusive
- Ignored
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External hardware
FTDI Cable
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | UART Rx | UART Tx | Tied Low |
| 1 | Tied Low | Tied Low | |
| 2 | Tied Low | Tied Low | |
| 3 | Tied Low | Tied Low | |
| 4 | Tied Low | Tied Low | |
| 5 | Tied Low | Tied Low | |
| 6 | Tied Low | Tied Low | |
| 7 | Tied Low | Tied Low |