Combinational loops with dividers to bring output frequency to <50kHz range
Select oscillator (pins 4-6) and mesaure frequency on one of output pins. Observe true random numbers at pin 7.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | generated clock | ||
| 1 | clock divided by 2^1 | ||
| 2 | shift register clk | clock divided by 2^2 | |
| 3 | shift register data | clock divided by 2^3 | |
| 4 | clock source id_0 | clock divided by 2^4 | |
| 5 | clock source id_1 | clock divided by 2^9 | |
| 6 | clock source id_2 | TRNG output | |
| 7 | Bit 11 of shift register |