ROTFPGA v2 is a reconfigurable logic circuit built from identical copies of the tile in Figure (a) containing a NAND gate, a D flip-flop and a buffer, with each tile individually rotated or reflected as described by the FPGA configuration. It is a port of the original ROTFPGA from Caravel to TinyTapeout. Porting the design required a 50-fold decrease in chip area which was achieved using a combination of cutting corners, heavy optimization and a few design changes. In particular:
Each tile can be configured in 8 possible orientations. Bits 0, 1 and 2 correspond to a diagonal, horizontal and vertical flip respectively. Any rotation or reflection can be described as a combination as shown in Figure (d). (The bottom row looks somewhat different, but we just rearranged the wires so that the inputs and outputs line up with the unmirrored tiles.)
Tiles are arranged in an 8×8 grid:
Figure (c) shows a 4×4 model of the tile grid. When the scan enable input is 0, the FPGA operates normally and each tile sets its flip-flop to the input it receives from one of the neighboring tiles according to its current rotation/reflection (black arrows). When scan enable is 1, it sets the flip-flop to the value received through the scan chain instead (grey arrows). This allows us to set the initial state of each flip-flop and also to query their state later for debugging. With some extra machinery it also allows us to change the rotations/reflections.
When the 2-bit configuration input is is 01, each cell updates its vertical flip bit to the current value of its flip-flop. Similarly, for 10 it sets the horizontal flip and for 11 it sets the diagonal flip. When configuration is 00, all three flip bits are latched and the orientation doesn’t change.
One can thus configure the FPGA by sending the sequence of all diagonal flip bits through the scan chain, then setting configuration to 11 and back to 00, then sending all horizontal flip bits, setting configuration to 10 and back to 00, and finally sending the vertical flip bits and setting configuration to 01 and back to 00.
Note that in order to save space the flip bits are stored in latches, not registers. Changing the configuration input from 00 to 11 or vice versa can cause a race condition where it is temporarily 01 or 10, overwriting the horizontal or vertical flip bits. Therefore one should configure the diagonal flips first.
The user design may intentionally or inadvertantly contain combinational loops such as ring oscillators. To help debug such designs, the chip has a loop breaker mechanism using a loop breaker enable input as well as a 2-bit loop breaker class input.
Tiles are assigned to loop breaker classes according to Figure (b). The loop breaker latches a tile output if and only if the following conditions are all met:
The loop breaker has the following properties:
Setting the active-low reset input to 0 has the following effect:
Follow the test suite in
|0||tile(0,0) left in||tile(7,0) right out||scan enable input|
|1||tile(0,1) left in||tile(7,1) right out||scan chain input|
|2||tile(0,2) left in||tile(7,2) right out||configuration input bit 0|
|3||tile(0,3) left in||tile(7,3) right out||configuration input bit 1|
|4||tile(0,4) left in||tile(7,4) right out||loop breaker enable input|
|5||tile(0,5) left in||tile(7,5) right out||loop breaker class input bit 0|
|6||tile(0,6) left in||tile(7,6) right out||loop breaker class input bit 1|
|7||tile(0,7) left in||tile(7,7) right out||scan chain output|