941 all-digital pll
941 : all-digital pll
- Author: Shrikrishna Kaje
- Description: RTL design of a fully programmable all-digital pll
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
Works at 2MHz using 50MHz clock as a sampling clock. However, it is programmable based on the inputs given
How to test
Step the frequency 2MHz by 0.5MHz and measure the lock time. Also measure the jitter present in 2MHz output
External hardware
Function generator, Oscilloscope, VCO
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | clk90 | dout[0] | fb_clk |
| 1 | clk_ref | dout[1] | dco_out |
| 2 | clr | dout[2] | pgm_value[0] |
| 3 | program | dout[3] | pgm_value[1] |
| 4 | out_sel | dout[4] | pgm_value[2] |
| 5 | param_sel[0] | sign | pgm_value[3] |
| 6 | param_sel[1] | pgm_value[4] | |
| 7 | param_sel[2] |