227 Conway's GoL
227 : Conway's GoL
- Author: nitelich
- Description: Conway's Game of Life with VGA out and GPIO field manip/randomize
- GitHub repository
- Open in 3D viewer
- Clock: 25175000 Hz
Conway's Game of Life
It's another implementation of Conway's Game of Life.
What's Different?
This implementation includes VGA output and field manipulation via GPIO.
The VGA output follows the Tiny VGA project's pinout, based on the Tiny Tapeout pinouts page. You'll need a Tiny VGA PMOD board to get VGA output. Standard 60Hz, 640x480px VGA outputs are generated by this module.
The field manipulation is vaguely modeled after a video game controller. A single cell is visibly selected on-screen, and the controller pins can be used to modify the selection and set/clear the selection. The following inputs are included:
- Standard directional pad (D-pad) for moving the selection
- Button for state selection (live/dead)
- Button to update the selected cell to the selected state
- Button to randomize the whole field. This uses a PSRNG based on an alternate sequence generator.
- Button to return the selection to (0, 0), which is the top-left of the screen.
Other Control Signals
In addition to the I/O for VGA and field control, the following control signals are given:
- Color advance inputs, allowing the foreground and background colors to be selected out of a sequence of sixteen. The default colors are black for background and cyan for foreground.
- Colors are based on 4-bit "web colors" list: White, Silver, Grey, Black, Red, Maroon, Yellow, Olive, Lime,Green, Aqua, Teal, Blue, Navy, Fuchsia, and Purple.
- Field update divisor, allowing the game of life update frequency to be lowered. By default, the update rate is one generation per vertical sync (60Hz). This 4-bit divisor allows for division by 1 through division by 16 (minimal update rate 3.75Hz).
- Single step mode, with step input. Single step mode allows for easy drawing of specific patterns using the field manipulation inputs.
Note that the input clock should be for standard VGA, 25.175MHz, as it is used to generate standard VGA signals.
Testing
Low level components of this module were tested using dedicated test benches (source not included here). The module as a whole was wrapped in the MiSTer core template and tested on the MiSTer FPGA (source and core RBF file not included here).
Local hardening was performed on a Debian 12 (Bookworm) virtual machine running on Windows via VirtualBox. Local hardening was used to tweak the tile size, acceptable area usage, and hold slack from their default values.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Foreground Next (on rising edge) | VGA R[1] | Selection Up (Input, on rising edge) |
| 1 | Background Next (on rising edge) | VGA G[1] | Selection Down (Input, on rising edge) |
| 2 | Free-run Divisor[0] | VGA B[1] | Selection Left (Input, on rising edge) |
| 3 | Free-run Divisor[1] | VGA VSync | Selection Right (Input, on rising edge) |
| 4 | Free-run Divisor[2] | VGA R[0] | Target State (Input) |
| 5 | Free-run Divisor[3] | VGA G[0] | Selection to Target State (Input, on rising edge) |
| 6 | External Hold | VGA B[0] | Randomize All (Input, on rising edge) |
| 7 | External Step (on rising edge) | VGA HSync | Selection to Origin (Input, on rising edge) |