747 8bit_up-down_counter
747 : 8bit_up-down_counter
- Author: Gopi Krishnan M
- Description: An 8-bit up/down counter that increments or decrements its value from 0 to 255 based on a control input
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
This project implements an 8-bit up/down counter in Verilog. The counter increments or decrements its value between 0 and 255 based on the up_down control signal:
up_down = 1→ counts upup_down = 0→ counts down
The counter only updates on the rising edge of the clk signal when the enable input is high. An active-low reset (rst_n) sets the counter to 0. The current counter value is output on the 8-bit uo_out bus.
Summary of signals:
ui[0]= enableui[1]= up/down controlui[2]= clock (clk)uo[0..7]= 8-bit counter output (q)
How to test
- Connect the
clkinput to a clock source (or simulation clock). - Drive
ui[0]high to enable counting. - Drive
ui[1]high to count up or low to count down. - Optionally, pull
rst_nlow to reset the counter to 0. - Observe the 8-bit output on
uo[0..7]to verify the counter value.
Simulation can be performed using any Verilog simulator (e.g., Icarus Verilog, ModelSim, or TinyTapeout simulation environment).
External hardware
Optionally, the output bus uo_out can be connected to LEDs, a logic analyzer, or other display modules to visualize the count.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | enable | q[0] | |
| 1 | up_down | q[1] | |
| 2 | clk | q[2] | |
| 3 | q[3] | ||
| 4 | q[4] | ||
| 5 | q[5] | ||
| 6 | q[6] | ||
| 7 | q[7] |