
Clk input is divided into 1/2, 1/4..., 1/256; which clock divider drives the output is selected with an 8:1 MUX with the pins S0, S1, S2
Connect a clock and test out the output by varying the MUX select switches
Needs external clock, 3 select switches and power
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | MUX_S0 | MUX_out | |
| 1 | |||
| 2 | MUX_S1 | ||
| 3 | MUX_S2 | ||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |