
This project implements a hardware-efficient Tsetlin Machine (TM) binary classifier optimized for ultra-low-power Edge AI. Unlike traditional neural networks that rely on power-hungry arithmetic multipliers and floating-point weights, this architecture uses pure digital logic and finite state machines to learn and classify data.
The machine processes a 4-bit binary input feature space and outputs a single binary classification. The internal architecture consists of:
The chip operates in two modes, controlled by the Mode pin (ui_in[5]):
ui_in[4]). It uses a deterministic implementation of Type I feedback (to reinforce correct patterns) and Type II feedback (to break incorrect patterns). The counters update synchronously on every positive clock edge.To operate the Tsetlin Machine, you will need to manually toggle the inputs or drive them with a microcontroller.
1. Initialization
rst_n to 0 to initialize all 32 internal automata to their default state (8).rst_n to 1 to begin normal operation.2. Training the Machine
ui_in[5] to 1.ui_in[3:0].ui_in[4].clk pin. The internal counters will increment or decrement based on the learning rules. Repeat this process for your training dataset.3. Running Inference
ui_in[5] to 0.ui_in[3:0].uo_out[0].For basic testing, no specialized external hardware is required.
However, because this chip is designed specifically for ultra-low-power Edge AI, it is ideally suited to be paired with external PMODs or custom sensor boards for real-world applications.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | feature_0 | predicted_class | |
| 1 | feature_1 | ||
| 2 | feature_2 | ||
| 3 | feature_3 | ||
| 4 | target_class | ||
| 5 | Train_mode (0=inference; 1=train) | ||
| 6 | |||
| 7 |